| commit | 7f5a1eeb24b6e3523d836cb0d3533fbb12f9fdf3 | [log] [tgz] |
|---|---|---|
| author | Paul Menzel <pmenzel@molgen.mpg.de> | Wed Dec 15 10:47:05 2021 +0100 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Thu Dec 16 14:17:36 2021 +0000 |
| tree | c1cfed28bc081c572f52fdc4933628d050b9c8f8 | |
| parent | 74d2218cc7c5b9d07528a2ffb3b727e52e688bd3 [diff] [blame] |
Spell *Boot Guard* with a space for official spelling
See for example Intel document *Secure the Network Infrastructure –
Secure Boot Methodologies* [1].
Change all occurrences with the command below:
$ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g'
[1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf
Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9ead46b..fd5ffd9 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c
@@ -247,7 +247,7 @@ /* * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address, + * or TXT/Boot Guard related data. Rather than report a base address, * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */