diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 1b402dc..55f2928 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -74,8 +74,7 @@
 
 	s3resume = southbridge_detect_s3_resume();
 
-	if (CONFIG(ELOG_BOOT_COUNT) && !s3resume)
-		boot_count_increment();
+	elog_boot_notify(s3resume);
 
 	post_code(0x38);