sb/intel/bd82x6x: Align some ME functions
This eliminates the differences in the first part of the file.
Change-Id: Ifb7d57da08e02664a28819e65bc8e9697ed38c4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42009
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index bc0a71e..ebb9db9 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -10,10 +10,10 @@
#include <acpi/acpi.h>
#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <string.h>
@@ -564,7 +564,7 @@
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = (u32*)(uintptr_t)res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);