commit 7e75f33de5a80d7a30d341149cd2ca13f2fe5423
author Kyösti Mälkki <kyosti.malkki@gmail.com> Sun Jun 14 12:23:04 2020 +0300
committer Angel Pons <th3fanbus@gmail.com> Tue Jun 16 10:19:35 2020 +0000
tree 9fa354d136baf1a36c92217524b2c1dec100f5ce
parent f71f3ae9c2ad6ea96be10764db001ebb5fc9ed0a

sb/intel/common/pmutil: Add dump_all_status()

Change-Id: I10582941afd68425603f6c4cadd228797cd098e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/southbridge/intel/common/smi.c

diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 9bf763d..913cce0 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -17,31 +17,30 @@
 	return lpc_get_pmbase();
 }
 
-static void smm_southbridge_enable(uint16_t pm1_events)
+static int smi_enabled(void)
 {
 	u32 smi_en;
-	u32 gpe0_en;
 
-	if (CONFIG(ELOG))
 	/* Log events from chipset before clearing */
+	if (CONFIG(ELOG))
 		pch_log_state();
 
 	printk(BIOS_DEBUG, "Initializing southbridge SMI...");
-
 	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase());
 
 	smi_en = read_pmbase32(SMI_EN);
 	if (smi_en & APMC_EN) {
 		printk(BIOS_INFO, "SMI# handler already enabled?\n");
-		return;
+		return 1;
 	}
-
 	printk(BIOS_DEBUG, "\n");
-	dump_smi_status(reset_smi_status());
-	dump_pm1_status(reset_pm1_status());
-	dump_gpe0_status(reset_gpe0_status());
-	dump_alt_gp_smi_status(reset_alt_gp_smi_status());
-	dump_tco_status(reset_tco_status());
+	return 0;
+}
+
+static void smm_southbridge_enable(uint16_t pm1_events)
+{
+	u32 smi_en;
+	u32 gpe0_en;
 
 	/* Disable GPE0 PME_B0 */
 	gpe0_en = read_pmbase32(GPE0_EN);
@@ -73,6 +72,10 @@
 
 void global_smi_enable(void)
 {
+	if (smi_enabled())
+		return;
+
+	dump_all_status();
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
 
@@ -97,22 +100,8 @@
 
 void smm_southbridge_clear_state(void)
 {
-	u32 smi_en;
-
-	if (CONFIG(ELOG))
-	/* Log events from chipset before clearing */
-		pch_log_state();
-
-	printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n");
-	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
-
-	smi_en = inl(get_pmbase() + SMI_EN);
-	if (smi_en & APMC_EN) {
-		printk(BIOS_INFO, "SMI# handler already enabled?\n");
+	if (smi_enabled())
 		return;
-	}
-
-	printk(BIOS_DEBUG, "\n");
 
 	/* Dump and clear status registers */
 	reset_smi_status();