AGESA f14/f15tn/f16kb: Factor out memory settings
We use the same values everywhere, so we might as well factor them out.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 4729577..1ac2266 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index d2bc4e7..5ea4c0c 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index a3cbb7e..05ac8c6 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -302,15 +302,4 @@
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 5f18c39..66d1a74 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index d3d65713..29668bc 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 53929b8..a97e8f0 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -302,15 +302,4 @@
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index d3d65713..29668bc 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 5f8700b..6fba259 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -197,16 +197,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c
index 99b6180..042fe59 100644
--- a/src/mainboard/asrock/imb-a180/buildOpts.c
+++ b/src/mainboard/asrock/imb-a180/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index a364982..fde272a 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -313,16 +313,5 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* AGESA nonsense: this header depends on the definitions above */
#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 38d302e..8bb0b80 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -303,16 +303,5 @@
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* Moving this include up will break AGESA. */
#include <PlatformInstall.h>
diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c
index 2bcabf4..b615353 100644
--- a/src/mainboard/bap/ode_e20XX/buildOpts.c
+++ b/src/mainboard/bap/ode_e20XX/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c
index d2bc4e7..5ea4c0c 100644
--- a/src/mainboard/biostar/a68n_5200/buildOpts.c
+++ b/src/mainboard/biostar/a68n_5200/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c
index b9a3efe..24f8da0 100644
--- a/src/mainboard/biostar/am1ml/buildOpts.c
+++ b/src/mainboard/biostar/am1ml/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index 8c34cd6..7fa480b 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 5f18c39..66d1a74 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
index 2bcabf4..b615353 100644
--- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
@@ -300,15 +300,4 @@
};
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index a649c73..9190968 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -314,15 +314,4 @@
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
#include <PlatformInstall.h>
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index e7ff996..8e90a08 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -346,16 +346,5 @@
};
#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* AGESA nonsense: this header depends on the definitions above */
#include <PlatformInstall.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index a20d133..1e81f5b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -190,19 +190,6 @@
#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */
#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */
-/**
- * The following definitions specify the default values for various parameters
- * in which there are no clearly defined defaults to be used in the common
- * file. The values below are based on product and BKDG content.
- */
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* AGESA nonsense: this header depends on the definitions above */
/* Instantiate all solution relevant data. */
#include <PlatformInstall.h>
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index f4993d6..fd1c977 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -346,16 +346,5 @@
};
#define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* AGESA nonsense: this header depends on the definitions above */
#include <PlatformInstall.h>
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 5f18c39..66d1a74 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 5f18c39..66d1a74 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index 4029bc3..c969d54 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -303,16 +303,5 @@
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* Moving this include up will break AGESA. */
#include <PlatformInstall.h>
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 639d605..a810559 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -191,16 +191,5 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
// Instantiate all solution relevant data.
#include <PlatformInstall.h>
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 2de9de5..883d509 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -583,7 +583,7 @@
#ifdef BLDCFG_VRM_SLEW_RATE
#define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
#else
- #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
@@ -613,7 +613,7 @@
#ifdef BLDCFG_VRM_NB_SLEW_RATE
#define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
#else
- #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_NB_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
@@ -722,7 +722,7 @@
#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
#define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
#else
- #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
+ #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#endif
#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
@@ -848,31 +848,31 @@
#ifdef BLDCFG_SCRUB_DRAM_RATE
#define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
#else
- #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
+ #define CFG_SCRUB_DRAM_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L2_RATE
#define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
#else
- #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
+ #define CFG_SCRUB_L2_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L3_RATE
#define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
#else
- #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
+ #define CFG_SCRUB_L3_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_IC_RATE
#define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
#else
- #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
+ #define CFG_SCRUB_IC_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_DC_RATE
#define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
#else
- #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
+ #define CFG_SCRUB_DC_RATE (0)
#endif
#ifdef BLDCFG_ECC_SYNC_FLOOD
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
index 63dae95..d769220 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
@@ -1758,7 +1758,7 @@
#ifdef BLDCFG_VRM_SLEW_RATE
#define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
#else
- #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
@@ -1820,7 +1820,7 @@
#ifdef BLDCFG_VRM_NB_SLEW_RATE
#define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
#else
- #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_NB_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_PLAT_NUM_IO_APICS
@@ -1928,7 +1928,7 @@
#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
#define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
#else
- #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
+ #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#endif
#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
@@ -2060,31 +2060,31 @@
#ifdef BLDCFG_SCRUB_DRAM_RATE
#define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
#else
- #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
+ #define CFG_SCRUB_DRAM_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L2_RATE
#define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
#else
- #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
+ #define CFG_SCRUB_L2_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L3_RATE
#define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
#else
- #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
+ #define CFG_SCRUB_L3_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_IC_RATE
#define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
#else
- #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
+ #define CFG_SCRUB_IC_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_DC_RATE
#define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
#else
- #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
+ #define CFG_SCRUB_DC_RATE (0)
#endif
#ifdef BLDCFG_ECC_SYNC_FLOOD
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
index 6c84bcb..ff5b91c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
@@ -747,7 +747,7 @@
#ifdef BLDCFG_VRM_SLEW_RATE
#define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
#else
- #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
@@ -789,7 +789,7 @@
#ifdef BLDCFG_VRM_NB_SLEW_RATE
#define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
#else
- #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
+ #define CFG_VRM_NB_SLEW_RATE (5000)
#endif
#ifdef BLDCFG_PLAT_NUM_IO_APICS
@@ -897,7 +897,7 @@
#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
#define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
#else
- #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
+ #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#endif
#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
@@ -1029,31 +1029,31 @@
#ifdef BLDCFG_SCRUB_DRAM_RATE
#define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
#else
- #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
+ #define CFG_SCRUB_DRAM_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L2_RATE
#define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
#else
- #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
+ #define CFG_SCRUB_L2_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_L3_RATE
#define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
#else
- #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
+ #define CFG_SCRUB_L3_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_IC_RATE
#define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
#else
- #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
+ #define CFG_SCRUB_IC_RATE (0)
#endif
#ifdef BLDCFG_SCRUB_DC_RATE
#define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
#else
- #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
+ #define CFG_SCRUB_DC_RATE (0)
#endif
#ifdef BLDCFG_ECC_SYNC_FLOOD