src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index f4b61de..aff62f2 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -737,7 +737,7 @@
printram("Hw MRS set is 0x%4x\n", reg16);
pci_write_config16(MCU, 0xcc, reg16);
/* Wait for MRS commands to be sent */
- while (pci_read_config8(MCU, 0xcc) & 1) ;
+ while (pci_read_config8(MCU, 0xcc) & 1);
}
/*
@@ -1114,7 +1114,7 @@
pci_write_config8(MCU, 0x71, reg8);
/* Wait for it */
- while (pci_read_config8(MCU, 0x71) & 0x10) ;
+ while (pci_read_config8(MCU, 0x71) & 0x10);
vx900_dram_exit_read_leveling(pinswap);
}
@@ -1146,7 +1146,7 @@
pci_mod_config8(MCU, 0x71, 0x03, 0x02);
/* Wait for calibration to complete */
- while (pci_read_config8(MCU, 0x71) & 0x02) ;
+ while (pci_read_config8(MCU, 0x71) & 0x02);
vx900_dram_exit_read_leveling(pinswap);
/* Restore the refresh counter */
@@ -1163,7 +1163,7 @@
/* Trigger calibration */
pci_mod_config8(MCU, 0x75, 0, 0x20);
/* Wait for calibration */
- while (pci_read_config8(MCU, 0x75) & 0x20) ;
+ while (pci_read_config8(MCU, 0x75) & 0x20);
}
/*
@@ -1192,7 +1192,7 @@
/* Trigger calibration */
pci_mod_config8(MCU, 0x75, 0, 0x02);
/* Wait for calibration */
- while (pci_read_config8(MCU, 0x75) & 0x02) ;
+ while (pci_read_config8(MCU, 0x75) & 0x02);
}
static void vx900_rxdqs_adjust(delay_range * dly)