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review.coreboot.org / coreboot / 7d6697d51c4452a5358344d43801335170e26e94
commit7d6697d51c4452a5358344d43801335170e26e94[log] [tgz]
authorFurquan Shaikh <furquan@google.com>Wed May 20 23:40:30 2020 -0700
committerPatrick Georgi <pgeorgi@google.com>Sat Jun 06 09:29:06 2020 +0000
tree00ded7eec78b7c429fea9b588a8b96a13bddc66b
parent459655abe7073d4bdbd36d7f1876eb73c1795768 [diff]
mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using gen_part_id.go

This change adds mem_list_variant.txt that contains the list of
memory parts used by halvor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: H9HKNNNCRMBVAR-NEH
Byte#    Current     New         Explanation
4        0x16        0x15        As per datasheet, density is 8Gb per
                                 logical channel. So value should be 0x15.
6        0xB9        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00. 2 channels 2
				 dies. Hence, 0x94
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
29,30    0xE0,0x0B   0xC0,0x08   As per datasheet, this corresponds to
                                 280ns in MTB units which is 0x08C0.
31,32    0xF0,0x05   0x60,0x04   As per datasheet, this corresponds to
                                 140ns in MTB units which is 0x0460.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: MT53E1G64D4SQ-046 WT:A
Byte#    Current     New         Explanation
5        0x21        0x29        As per datasheet, this part has 17row
                                 address bits and 10column address
                                 bits. This results in 0x29.
6        0xB9        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00. 2 channels,
				 2 dies. Hence, 0x94.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

BUG=b:147321551,b:155423877

Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
3 files changed
tree: 00ded7eec78b7c429fea9b588a8b96a13bddc66b
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.