tree d481ad50ffedbbccc7e051c092849cb760509d9c
parent 1d8d99bfd93602bbcc4f318f384a93cdad045705
author Sam Lewis <sam.vr.lewis@gmail.com> 1596712402 +1000
committer Arthur Heymans <arthur@aheymans.xyz> 1617103309 +0000

mb/ti/beaglebone: Initialize DDR3

Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.

TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.

Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>