commit 7c92712cf0fdfd85fa518cda57e19d1cd7097108
author Tim Crawford <tcrawford@system76.com> Fri Dec 30 10:05:38 2022 -0700
committer Martin L Roth <gaumless@gmail.com> Thu Jan 05 17:55:17 2023 +0000
tree 0faf94fe1f786c953c4a9dd5cb7f982963d875b2
parent 06545e0744e322b2148f4cb52eb976737754e65b

mb/system76/tgl-u: Add FSP-S configs per variant

Configure CPU PCIe RP and IOM per variant.

Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

src/mainboard/system76/tgl-u/Makefile.inc

diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc
index 845c39a..ca14835 100644
--- a/src/mainboard/system76/tgl-u/Makefile.inc
+++ b/src/mainboard/system76/tgl-u/Makefile.inc
@@ -12,5 +12,6 @@
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 
 SPD_SOURCES = samsung-M471A1G44AB0-CWE

src/mainboard/system76/tgl-u/ramstage.c

diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c
index d4cb898..a01391a 100644
--- a/src/mainboard/system76/tgl-u/ramstage.c
+++ b/src/mainboard/system76/tgl-u/ramstage.c
@@ -9,12 +9,6 @@
 	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
 }
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	// Disable AER to fix suspend failing with some SSDs.
-	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
-}
-
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();

src/mainboard/system76/tgl-u/variants/darp7/ramstage.c

diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
new file mode 100644
index 0000000..a60587d
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}

src/mainboard/system76/tgl-u/variants/galp5/ramstage.c

diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
new file mode 100644
index 0000000..a60587d
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}

src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c

diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
new file mode 100644
index 0000000..2064836
--- /dev/null
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+}