commit 7c66d39a0b94e894a56453e0624e976bbbec8850
author Martin Roth <gaumless@gmail.com> Thu Feb 02 17:23:46 2023 -0700
committer Felix Held <felix-coreboot@felixheld.de> Sat Feb 04 03:23:24 2023 +0000
tree bccf0d4befc805b8360b3cdc1e88ef6385074e2e
parent 10c43a2c2e0a68a80bd4fc92732cde037b1d4a34

soc/amd: Use common reset code for PCO SoC

This switches the Picasso SoC to use the common reset code.

Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET
flag.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/Kconfig

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index a0254e9..d34b2ab 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -50,6 +50,7 @@
 	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	select SOC_AMD_COMMON_BLOCK_RESET
 	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
@@ -61,6 +62,7 @@
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
 	select SOC_AMD_COMMON_FSP_DMI_TABLES
+	select SOC_AMD_SUPPORTS_WARM_RESET
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR4

src/soc/amd/picasso/Makefile.inc

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 50fc62c..e7ed68e 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -12,19 +12,16 @@
 bootblock-y += early_fch.c
 bootblock-y += gpio.c
 bootblock-y += i2c.c
-bootblock-y += reset.c
 bootblock-y += uart.c
 
 romstage-y += fsp_m_params.c
 romstage-y += gpio.c
 romstage-y += i2c.c
-romstage-y += reset.c
 romstage-y += romstage.c
 romstage-y += uart.c
 
 verstage-y += i2c.c
 verstage_x86-y += gpio.c
-verstage_x86-y += reset.c
 verstage_x86-y += uart.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -38,7 +35,6 @@
 ramstage-y += i2c.c
 ramstage-y += mca.c
 ramstage-y += pcie_gpp.c
-ramstage-y += reset.c
 ramstage-y += root_complex.c
 ramstage-y += sata.c
 ramstage-y += soc_util.c

src/soc/amd/picasso/reset.c

diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c
deleted file mode 100644
index 8181d90..0000000
--- a/src/soc/amd/picasso/reset.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <cf9_reset.h>
-#include <reset.h>
-#include <soc/southbridge.h>
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/reset.h>
-
-void do_cold_reset(void)
-{
-	/* De-assert and then assert all PwrGood signals on CF9 reset. */
-	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
-		TOGGLE_ALL_PWR_GOOD);
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_warm_reset(void)
-{
-	/* Assert reset signals only. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_board_reset(void)
-{
-	/* TODO: Would a warm_reset() suffice? */
-	do_cold_reset();
-}