diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index b1abf5e..0735ceaa 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -17,29 +17,29 @@
 
 #include <stdint.h>
 
-#define BASEFREQ 133
-#define tDLLK 512
+#define BASEFREQ	133
+#define tDLLK		512
 
-#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
-#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
+#define IS_SANDY_CPU(x)    ((x & 0xffff0) == 0x206a0)
+#define IS_SANDY_CPU_C(x)  ((x & 0xf) == 4)
 #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
 #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
 #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
 
-#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
+#define IS_IVY_CPU(x)   ((x & 0xffff0) == 0x306a0)
 #define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
 #define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
 #define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
 #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
 
-#define NUM_CHANNELS 2
-#define NUM_SLOTRANKS 4
-#define NUM_SLOTS 2
-#define NUM_LANES 8
+#define NUM_CHANNELS	2
+#define NUM_SLOTRANKS	4
+#define NUM_SLOTS	2
+#define NUM_LANES	8
 
 /* FIXME: Vendor BIOS uses 64 but our algorithms are less
    performant and even 1 seems to be enough in practice.  */
-#define NUM_PATTERNS 4
+#define NUM_PATTERNS	4
 
 typedef struct odtmap_st {
 	u16 rttwr;
@@ -51,24 +51,24 @@
 } dimm_info;
 
 struct ram_rank_timings {
-	/* ROUNDT_LAT register. One byte per slotrank. */
+	/* ROUNDT_LAT register: One byte per slotrank */
 	u8 roundtrip_latency;
 
-	/* IO_LATENCY register. One nibble per slotrank. */
+	/* IO_LATENCY register: One nibble per slotrank */
 	u8 io_latency;
 
-	/* Phase interpolator coding for command and control. */
+	/* Phase interpolator coding for command and control */
 	int pi_coding;
 
 	struct ram_lane_timings {
-		/* lane register offset 0x10.  */
-		u16 timA;	/* bits 0 - 5, bits 16 - 18 */
-		u8 rising;	/* bits 8 - 14 */
-		u8 falling;	/* bits 20 - 26.  */
+		/* Lane register offset 0x10 */
+		u16 timA;	/* bits  0 -  5, bits 16 - 18 */
+		u8 rising;	/* bits  8 - 14 */
+		u8 falling;	/* bits 20 - 26 */
 
-		/* lane register offset 0x20.  */
-		int timC;	/* bit 0 - 5, 19.  */
-		u16 timB;	/* bits 8 - 13, 15 - 17.  */
+		/* Lane register offset 0x20 */
+		int timC;	/* bits 0 -  5, 19 */
+		u16 timB;	/* bits 8 - 13, 15 - 17 */
 	} lanes[NUM_LANES];
 };
 
@@ -82,7 +82,7 @@
 	u8 base_freq;
 
 	u16 cas_supported;
-	/* tLatencies are in units of ns, scaled by x256 */
+	/* Latencies are in units of ns, scaled by x256 */
 	u32 tCK;
 	u32 tAA;
 	u32 tWR;
@@ -97,8 +97,8 @@
 	u32 tCWL;
 	u32 tCMD;
 	/* Latencies in terms of clock cycles
-	 * They are saved separately as they are needed for DRAM MRS commands */
-	u8 CAS;			/* CAS read latency */
+	   They are saved separately as they are needed for DRAM MRS commands */
+	u8 CAS;			/* CAS read  latency */
 	u8 CWL;			/* CAS write latency */
 
 	u32 tREFI;
@@ -110,7 +110,7 @@
 	u32 tXP;
 	u32 tAONPD;
 
-	/* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer. */
+	/* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */
 	u16 mdll_wake_delay;
 
 	u8 rankmap[NUM_CHANNELS];
@@ -135,7 +135,6 @@
 	dimm_info info;
 } ramctr_timing;
 
-#define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 #define SOUTHBRIDGE	PCI_DEV(0, 0x1f, 0)
 
 #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
@@ -149,8 +148,8 @@
 #define MAX_CAS 18
 #define MIN_CAS 4
 
-#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
-#define GET_ERR_CHANNEL(x) (x>>16)
+#define MAKE_ERR		((channel << 16) | (slotrank << 8) | 1)
+#define GET_ERR_CHANNEL(x)	(x >> 16)
 
 u8 get_CWL(u32 tCK);
 void dram_mrscommands(ramctr_timing *ctrl);
@@ -174,17 +173,14 @@
 void write_controller_mr(ramctr_timing *ctrl);
 int channel_test(ramctr_timing *ctrl);
 void set_scrambling_seed(ramctr_timing *ctrl);
-void set_4f8c(void);
+void set_wmm_behavior(void);
 void prepare_training(ramctr_timing *ctrl);
-void set_4008c(ramctr_timing *ctrl);
+void set_read_write_timings(ramctr_timing *ctrl);
 void set_normal_operation(ramctr_timing *ctrl);
 void final_registers(ramctr_timing *ctrl);
 void restore_timings(ramctr_timing *ctrl);
 
-int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot,
-		int s3_resume, int me_uma_size);
-
-int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot,
-		int s3_resume, int me_uma_size);
+int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
+int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
 
 #endif