nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 6a3156e..ab2a21c 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -16,36 +16,34 @@
#include <device/pci_ops.h>
#include "sandybridge.h"
-#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
-
void intel_sandybridge_finalize_smm(void)
{
- pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
- pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
- pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK);
- pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, TOUUD, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, BDSM, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, BGSM, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0);
- pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0);
+ pci_or_config16(HOST_BRIDGE, GGC, 1 << 0);
+ pci_or_config16(HOST_BRIDGE, PAVPC, 1 << 2);
+ pci_or_config32(HOST_BRIDGE, DPR, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, MESEG_MASK, MELCK);
+ pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
- MCHBAR32_OR(MMIO_PAVP_CTL, 1 << 0); /* PAVP */
- MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */
- MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
- MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
- MCHBAR32_OR(0x6800, 1 << 31);
- MCHBAR32_OR(0x7000, 1 << 31);
- MCHBAR32_OR(0x77fc, 1 << 0);
+ MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */
+ MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */
+ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
+ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
+ MCHBAR32_OR(REQLIM, 1 << 31);
+ MCHBAR32_OR(DMIVCLIM, 1 << 31);
+ MCHBAR32_OR(CRDTLCK, 1 << 0);
/* Memory Controller Lockdown */
MCHBAR8(MC_LOCK) = 0x8f;
/* Read+write the following */
- MCHBAR32(0x6030) = MCHBAR32(0x6030);
- MCHBAR32(0x6034) = MCHBAR32(0x6034);
- MCHBAR32(0x6008) = MCHBAR32(0x6008);
+ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM);
+ MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);
+ MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID);
}