soc/intel/common/block/p2sb: Add helper function to enable BAR
This patch creates a new helper function to enable P2SB BAR.
`p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F)
and BAR address (combining high and low base addresses).
BUG=b:224325352
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 94db33d..1b0c080 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -18,13 +18,7 @@
void p2sb_enable_bar(void)
{
- /* Enable PCR Base address in PCH */
- pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR);
- pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0);
-
- /* Enable P2SB MSE */
- pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ p2sb_dev_enable_bar(PCH_DEV_P2SB, P2SB_BAR);
}
/*