mb/facebook/monolith: Add Facebook Monolith

The board is booting Linux and has been briefly tested.

SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.

BUG=N/A
TEST=tested on Facebook Monolith

Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md
new file mode 100644
index 0000000..9b9f33b
--- /dev/null
+++ b/Documentation/mainboard/facebook/monolith.md
@@ -0,0 +1,78 @@
+# Facebook Monolith
+
+This page describes how to run coreboot on the Facebook Monolith.
+
+Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully 
+tested yet.
+
+## Required blobs
+
+This board currently requires:
+fsp blobs	3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd
+		3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd
+
+Microcode	3rdparty/intel-microcode/intel-ucode
+
+## Flashing coreboot
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
+Specifically, it's a Winbond W25Q128JVSIQ (3.3V).
+
+The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip.
+Specifically, it's a Winbond W25Q128JVSIM (3.3V).
+
+Flashing of these devices is very difficult, disassembling the system destroys the cooling
+solution. Wires need to be connected to be able to flash using an external programmer.
+
+## Known issues
+
+- None
+
+## Untested
+
+- Hardware monitor
+- SDIO
+- Full Embedded Controller support
+- eMMC
+- SATA
+
+## Working
+
+- USB
+- Gigabit Ethernet
+- Graphics (Using FSP GOP)
+- flashrom
+- PCIe
+- EC serial port
+- SMBus
+- Initialization with FSP
+- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
+- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
+
+All of the above has been briefly tested by booting Linux from the TianoCore payload.
+SeaBios has been checked to the extend that it runs to the boot selection and provides display
+output.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Kaby Lake U                                 |
++------------------+--------------------------------------------------+
+| CPU              | Intel i3-7100U                                   |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE8256                                          |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
+[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 60302cb..038689d 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -32,6 +32,7 @@
 ## Facebook
 
 - [FBG-1701](facebook/fbg1701.md)
+- [Monolith](facebook/monolith.md)
 
 ## Foxconn
 
diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig
new file mode 100644
index 0000000..3261661
--- /dev/null
+++ b/src/mainboard/facebook/monolith/Kconfig
@@ -0,0 +1,90 @@
+if BOARD_FACEBOOK_MONOLITH
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select SOC_INTEL_KABYLAKE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select INTEL_GMA_HAVE_VBT
+
+config CBFS_SIZE
+	hex "CBFS_SIZE"
+	default 0x00900000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAINBOARD_DIR
+	string
+	default "facebook/monolith"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Monolith"
+
+config MAINBOARD_FAMILY
+	string
+	default "Facebook Monolith"
+
+config MAX_CPUS
+	int
+	default 4
+
+config IFD_BIN_PATH
+	string
+	depends on HAVE_IFD_BIN
+	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+
+config ME_BIN_PATH
+	string
+	depends on HAVE_ME_BIN
+	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
+
+config GBE_BIN_PATH
+	string
+	depends on HAVE_GBE_BIN
+	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+	hex
+	default 0xd00
+
+config DIMM_SPD_SIZE
+	int
+	default 512  #DDR4
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config DIMM_MAX
+	int
+	default 2
+
+config TPM_INIT
+	bool
+	default n
+
+config MAINBOARD_SUPPORTS_SKYLAKE_CPU
+	bool
+	default n
+
+config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
+	bool
+	default n
+
+config RW_REGION_ONLY
+	string "Files in RW only"
+
+config VBOOT_ENABLE_CBFS_FALLBACK
+	bool
+	default y
+	depends on VBOOT
+
+endif
diff --git a/src/mainboard/facebook/monolith/Kconfig.name b/src/mainboard/facebook/monolith/Kconfig.name
new file mode 100644
index 0000000..865aa2f
--- /dev/null
+++ b/src/mainboard/facebook/monolith/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_FACEBOOK_MONOLITH
+	bool "Facebook Monolith"
diff --git a/src/mainboard/facebook/monolith/Makefile.inc b/src/mainboard/facebook/monolith/Makefile.inc
new file mode 100644
index 0000000..0cccd26
--- /dev/null
+++ b/src/mainboard/facebook/monolith/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2016 Intel Corporation.
+## Copyright (C) 2019 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += com_init.c
+
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl
new file mode 100644
index 0000000..5ea95b4
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/dptf.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/ec.asl
diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl
new file mode 100644
index 0000000..2a3ad59
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+/*
+ * Onboard CPLD
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	Device (CPLD)		/* Onboard CPLD */
+	{
+		Name(_HID, EISAID("PNP0C01"))
+		Name(_CRS, ResourceTemplate()
+		{
+			/* Reserve 0x280 to 0x2BF for the CPLD */
+			FixedIO (0x0280, 0x40)
+			IRQNoFlags () {7}
+		})
+	}
+}
diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl
new file mode 100644
index 0000000..0f5790d
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/superio.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	Name (_CRS, ResourceTemplate ()
+	{
+		FixedIO (0x03F8, 0x08)
+		FixedIO (0x6E, 0x02)
+		IRQNoFlags () {4}
+	})
+
+	Name (_PRS, ResourceTemplate ()
+	{
+		StartDependentFn (0, 0) {
+			FixedIO (0x03F8, 0x08)
+			FixedIO (0x6E, 0x02)
+			IRQNoFlags () {4}
+		}
+		EndDependentFn ()
+	})
+}
diff --git a/src/mainboard/facebook/monolith/acpi_tables.c b/src/mainboard/facebook/monolith/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi_tables.c
diff --git a/src/mainboard/facebook/monolith/board_info.txt b/src/mainboard/facebook/monolith/board_info.txt
new file mode 100644
index 0000000..c58669c
--- /dev/null
+++ b/src/mainboard/facebook/monolith/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Facebook
+Board name: Monolith System
+Category: misc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout
new file mode 100644
index 0000000..04b2e15
--- /dev/null
+++ b/src/mainboard/facebook/monolith/cmos.layout
@@ -0,0 +1,121 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2016 Intel Corporation.
+## Copyright (C) 2019 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+# reboot_counter reserved for core, not used by platform.
+388          4       h       0        reboot_counter
+#390          2       r       0        unused
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392          3       r       0        unused
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+#400          1       e       2        unused
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#416        568       r        0       unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c
new file mode 100644
index 0000000..f19aba3
--- /dev/null
+++ b/src/mainboard/facebook/monolith/com_init.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include "onboard.h"
+
+#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable the serial port inside the EC */
+	pnp_set_logical_device(SERIAL_DEV);
+	pnp_set_enable(SERIAL_DEV, 1);
+}
diff --git a/src/mainboard/facebook/monolith/data.vbt b/src/mainboard/facebook/monolith/data.vbt
new file mode 100644
index 0000000..d2c3e6c
--- /dev/null
+++ b/src/mainboard/facebook/monolith/data.vbt
Binary files differ
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
new file mode 100644
index 0000000..b5e3191
--- /dev/null
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -0,0 +1,247 @@
+chip soc/intel/skylake
+
+	# Enable deep Sx states
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	# CPLD host command ranges are in 0x280-0x2BF
+	# EC PNP registers are at 0x6e and 0x6f
+	register "gen1_dec" = "0x003c0281"
+	register "gen3_dec" = "0x0004006d"
+
+	# LPC serial IRQ
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable DPTF
+	register "dptf_enable" = "0"
+
+	# FSP Configuration
+	register "EnableAzalia" = "0"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
+	register "SaGv" = "SaGv_Enabled"
+	register "SaImguEnable" = "0"
+	register "Cio2Enable" = "0"
+	register "PmTimerDisabled" = "1"
+	register "HeciEnabled" = "0"
+	register "EnableLan" = "1"
+
+	register "EnableSata" = "1"
+		register "SataSalpSupport" = "1"
+		register "SataPortsEnable" = "{ \
+			[0]	= 1, \
+			[1]	= 0, \
+			[2]	= 0, \
+			[3]	= 0, \
+			[4]	= 0, \
+			[5]	= 0, \
+			[6]	= 0, \
+			[7]	= 0, \
+		}"
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+	register "PmConfigSlpS3MinAssert" = "2"
+
+	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+	register "PmConfigSlpS4MinAssert" = "4"
+
+	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+	register "PmConfigSlpSusMinAssert" = "3"
+
+	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+	register "PmConfigSlpAMinAssert" = "3"
+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-------+-------+-------+-------+
+	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+	#+----------------+-------+-------+-------+-------+
+	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
+	#| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
+	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
+	#| Psi3Enable     | 1     | 1     | 1     | 1     |
+	#| Psi4Enable     | 1     | 1     | 1     | 1     |
+	#| ImonSlope      | 0     | 0     | 0     | 0     |
+	#| ImonOffset     | 0     | 0     | 0     | 0     |
+	#| IccMax         | 7A    | 34A   | 35A   | 35A   |
+	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+	#+----------------+-------+-------+-------+-------+
+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20), \
+		.psi2threshold = VR_CFG_AMP(5), \
+		.psi3threshold = VR_CFG_AMP(1), \
+		.psi3enable = 1, \
+		.psi4enable = 1, \
+		.imon_slope = 0, \
+		.imon_offset = 0, \
+		.icc_max = VR_CFG_AMP(7), \
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20), \
+		.psi2threshold = VR_CFG_AMP(5), \
+		.psi3threshold = VR_CFG_AMP(1), \
+		.psi3enable = 1, \
+		.psi4enable = 1, \
+		.imon_slope = 0, \
+		.imon_offset = 0, \
+		.icc_max = VR_CFG_AMP(34), \
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20), \
+		.psi2threshold = VR_CFG_AMP(5), \
+		.psi3threshold = VR_CFG_AMP(1), \
+		.psi3enable = 1, \
+		.psi4enable = 1, \
+		.imon_slope = 0, \
+		.imon_offset = 0, \
+		.icc_max = VR_CFG_AMP(35),\
+		.voltage_limit = 1520 \
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1, \
+		.psi1threshold = VR_CFG_AMP(20), \
+		.psi2threshold = VR_CFG_AMP(5), \
+		.psi3threshold = VR_CFG_AMP(1), \
+		.psi3enable = 1, \
+		.psi4enable = 1, \
+		.imon_slope = 0, \
+		.imon_offset = 0, \
+		.icc_max = VR_CFG_AMP(35), \
+		.voltage_limit = 1520 \
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+	# Enable Root ports.
+	# PCIE Port 1 disabled
+	# PCIE Port 2 disabled
+
+	# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
+	register "PcieRpEnable[2]" = "1"
+	# Disable CLKREQ#
+	register "PcieRpClkReqSupport[2]" = "0"
+
+	# PCIE Port 4 disabled
+	# PCIE Port 5 x1 -> MODULE i219
+
+	# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpClkReqSupport[5]" = "0"
+
+	# PCIE Port 7 Disabled
+	# PCIE Port 8 Disabled
+
+	# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
+	register "PcieRpEnable[8]" = "1"
+	# Disable CLKREQ#
+	register "PcieRpClkReqSupport[8]" = "0"
+	# Use Hot Plug subsystem
+	register "PcieRpHotPlug[8]" = "1"
+
+	# USB 2.0 Enable all ports
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 2
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"		# USB3_TYPE-A Port 1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB3_TYPE-A Port 2
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 1
+	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# M2 Port
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Disabled
+	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# Audio board
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Disabled
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Disabled
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"		# Disabled
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"		# Disabled
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"		# Disabled
+
+	# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 2
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 1
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 2
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 1
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"		# Disabled
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"		# Disabled
+
+	register "SsicPortEnable" = "0"
+
+	# Must leave UART0 enabled or SD/eMMC will not work as PCI
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoPci, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+	}"
+
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end #
+		device pci 08.0 on  end # Gaussian Mixture Model
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 on  end # USB xDCI (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 17.0 on  end # SATA
+		device pci 1c.2 on  end # PCI Express Port 3 x1 baseboard WWAN
+		device pci 1c.5 on  end # PCI Express Port 6 x1 baseboard i210
+		device pci 1d.0 on  end # PCI Express Port 9 x4 FPGA
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.4 on  end # eMMC
+		device pci 1e.5 off end # SDIO
+		device pci 1f.0 on  # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Bridge
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 on  end # GbE
+	end
+end
diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl
new file mode 100644
index 0000000..2f00110
--- /dev/null
+++ b/src/mainboard/facebook/monolith/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/skylake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/skylake/acpi/systemagent.asl>
+			#include <soc/intel/skylake/acpi/pch.asl>
+		}
+
+		// Dynamic Platform Thermal Framework
+		#include "acpi/dptf.asl"
+	}
+
+	// Chipset specific sleep states
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h
new file mode 100644
index 0000000..65300ff
--- /dev/null
+++ b/src/mainboard/facebook/monolith/gpio.h
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI		GPE0_DW2_16
+#define EC_SMI_GPI		GPP_E15
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* PCH_RCIN */		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
+/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
+/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
+/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
+/* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PM_SLP_S0ix_N */	PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
+///* PIRQA# */	        PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+/* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* LPC_CLK */		PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
+/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
+/* SLEEP */	        PAD_CFG_NC(GPP_A11),	/* available on the module not used here */
+/* ISH_KB_PROX_INT */	PAD_CFG_NC(GPP_A12),
+/* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_STAT */	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* SUSACK_R_N */	PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
+/* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+/* SD_PWR_EN */		PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ISH_GP0 */		PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */		PAD_CFG_NC(GPP_A19),
+/* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */		PAD_CFG_NC(GPP_A23),
+/* V0.85A_VID0 */	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+/* V0.85A_VID1 */	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+/* GP_VRALERTB */	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+/* CPU_GP2 */	        PAD_CFG_NC(GPP_B3),
+/* CPU_GP2 */	        PAD_CFG_NC(GPP_B4),
+/* CLK_REQ_SLOT0 */	PAD_CFG_NC(GPP_B5),
+/* CLK_REQ_SLOT1 */	PAD_CFG_NC(GPP_B6),
+/* CLK_REQ_SLOT2 */	PAD_CFG_NC(GPP_B7),
+/* CLK_REQ_SLOT3 */	PAD_CFG_NC(GPP_B8),
+/* CLK_REQ_SLOT4 */	PAD_CFG_NC(GPP_B9),
+/* CLK_REQ_SLOT5 */	PAD_CFG_NC(GPP_B10),
+/* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* PCH_SPKR */	    PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+/* GSPI0_CS# */		/* GPP_B15 */
+/* GSPI0_CLK */	    PAD_CFG_NC(GPP_B16),
+/* GSPI0_MISO */	PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */	PAD_CFG_NC(GPP_B18),
+/* GSPI1_CS */		PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+/* GSPI1_CLK */		PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
+/* GSPI1_MISO */	PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
+/* GSPI1_MOSI */	PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
+///* CB_OVT# */	        PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
+/* SML1ALERT# */	PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST),
+/* SMB_CLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */		PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
+/* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 1, DEEP),
+/* SML0_CLK */		PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0DATA */		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+///* SML0ALERT# */	PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST),
+/* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
+/* SML1_CLK */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* SML1_DATA */		PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
+/* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* UART0_RTS */		PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS */		PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* UART1_RXD */		PAD_CFG_NC(GPP_C12),
+/* UART1_TXD */		PAD_CFG_NC(GPP_C13),
+/* UART1_RTS */		PAD_CFG_NC(GPP_C14),
+/* UART1_CTS */		PAD_CFG_NC(GPP_C15),
+/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
+/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
+/* I2C1_SDA */		PAD_CFG_NC(GPP_C18),
+/* I2C1_SCL */		PAD_CFG_NC(GPP_C19),
+/* UART2_RXD */		PAD_CFG_NC(GPP_C20),
+/* UART2_TXD */		PAD_CFG_NC(GPP_C21),
+///* EC_SMI */		PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
+///* EC_SCI */		PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
+/* EC_SCI# not used */	PAD_CFG_NC(GPP_C22),
+/* EC_SMI# not used */	PAD_CFG_NC(GPP_C23),
+/* SPI1_CS */		PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+/* SPI1_CLK */		PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+/* SPI1_MISO */		PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+/* SPI1_MOSI */		PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+/* CAM_FLASH_STROBE */	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+/* ISH_I2C0_SDA */	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+/* ISH_I2C0_SCL */	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+/* ISH_I2C1_SDA */	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+/* ISH_I2C1_SCL */	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+/* GPP_D9 */		PAD_CFG_NC(GPP_D9),
+/* GPP_D10 */	    PAD_CFG_NC(GPP_D10),
+/* GPP_D11 */	    PAD_CFG_NC(GPP_D11),
+/* GPP_D12 */	    PAD_CFG_NC(GPP_D12),
+/* ISH_UART0_RXD */	PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */	PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS */	PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS */	PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK_1 */	PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA_1 */	PAD_CFG_NC(GPP_D18),
+/* DMIC_CLK_0 */	PAD_CFG_NC(GPP_D19),
+/* DMIC_DATA_0 */	PAD_CFG_NC(GPP_D20),
+/* SPI1_D2 */		PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+/* SPI1_D3 */		PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+/* I2S_MCLK */		PAD_CFG_NC(GPP_D23),
+///* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
+/* GPP_E0 */	    PAD_CFG_NC(GPP_E0),
+/* GPP_E1 */	    PAD_CFG_NC(GPP_E1),
+/* GPP_E2 */		PAD_CFG_NC(GPP_E2),
+/* GPP_E3 */	    PAD_CFG_NC(GPP_E3),
+/* SATA_DEVSLP0 */	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+/* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+/* SATA_DEVSLP2 */	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+/* GPP_E7 */	    PAD_CFG_NC(GPP_E7),
+/* SATALED# */		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */		PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST),
+/* DDI1_HPD */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* DDI3_HPD */		PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+/* DDI4_HPD */		PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+/* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
+/* DDPD_CTRLCLK */	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+/* DDPD_CTRLDATA */	PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1),
+/* I2S2_SCLK */		PAD_CFG_NC(GPP_F0),
+/* I2S2_SFRM */		PAD_CFG_NC(GPP_F1),
+/* I2S2_TXD */		PAD_CFG_NC(GPP_F2),
+/* I2S2_RXD */		PAD_CFG_NC(GPP_F3),
+/* I2C2_SDA */		PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */		PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */		PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */		PAD_CFG_NC(GPP_F8),
+/* I2C4_SDA */		PAD_CFG_NC(GPP_F9),
+/* ISH_I2C2_SDA */	PAD_CFG_NC(GPP_F10),
+/* ISH_I2C2_SCL */	PAD_CFG_NC(GPP_F11),
+/* EMMC_CMD */		PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* GPP_F23 */	    PAD_CFG_NC(GPP_F23),
+/* SD_CMD */		PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */		PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */		PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */		PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */		PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */		PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */		    PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
+/* PCH_BATLOW */	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* AC_PRESENT */	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* PCH_WAKE */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* PCH_PWRBTN */	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7 */		    PAD_CFG_NC(GPD7),
+/* PM_SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+/* PM_SLP_S5# */	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+};
+
+#endif
+#endif
diff --git a/src/mainboard/facebook/monolith/mainboard.c b/src/mainboard/facebook/monolith/mainboard.c
new file mode 100644
index 0000000..3d6532e
--- /dev/null
+++ b/src/mainboard/facebook/monolith/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+
+/*
+ * Declare the resources we are using
+ */
+static void mainboard_reserve_resources(struct device *dev)
+{
+	unsigned int idx = 0;
+	struct resource *res;
+
+	/*
+	 * CPLD: Reserve the IRQ here all others are within the default LPC
+	 * range 0 to 1000h
+	 */
+	res = new_resource(dev, idx++);
+	res->base = 0x7;
+	res->size = 0x1;
+	res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+/*
+ * mainboard_enable is executed as first thing after
+ * enumerate_buses().
+ */
+static void mainboard_enable(struct device *dev)
+{
+	mainboard_reserve_resources(dev);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/facebook/monolith/onboard.h b/src/mainboard/facebook/monolith/onboard.h
new file mode 100644
index 0000000..68b5fea
--- /dev/null
+++ b/src/mainboard/facebook/monolith/onboard.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define ITE8528_CMD_PORT	0x6E
+#define ITE8528_DATA_PORT	0x6F
+
+#endif
diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c
new file mode 100644
index 0000000..bed1049
--- /dev/null
+++ b/src/mainboard/facebook/monolith/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	params->CdClock = 3;
+}
diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c
new file mode 100644
index 0000000..7c54708
--- /dev/null
+++ b/src/mainboard/facebook/monolith/romstage.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2018 Intel Corporation.
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include "spd/spd.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+	struct spd_block blk = {
+		.addr_map = { 0x50, 0x52, },
+	};
+
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = 1;
+	get_spd_smbus(&blk);
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+	mupd->FspmTestConfig.DmiVc1 = 1;
+}
diff --git a/src/mainboard/facebook/monolith/spd/Makefile.inc b/src/mainboard/facebook/monolith/spd/Makefile.inc
new file mode 100644
index 0000000..b4b42f7
--- /dev/null
+++ b/src/mainboard/facebook/monolith/spd/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+## Copyright (C) 2019 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h
new file mode 100644
index 0000000..f2b6f2a
--- /dev/null
+++ b/src/mainboard/facebook/monolith/spd/spd.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define RCOMP_TARGET_PARAMS	0x5
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c
new file mode 100644
index 0000000..5ccc810
--- /dev/null
+++ b/src/mainboard/facebook/monolith/spd/spd_util.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+	/* DQ byte map */
+	const u8 dq_map[2][12] = {
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+	/* DQS CPU<>DRAM map */
+	const u8 dqs_map[2][8] = {
+		{ 0, 1, 3, 2, 4, 5, 6, 7 },
+		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
+	memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 200, 81, 162 };
+	memcpy(rcomp_ptr, RcompResistor,
+		 sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+	/* Rcomp target */
+	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+		100, 40, 40, 23, 40 };
+
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd
new file mode 100644
index 0000000..fad0f97
--- /dev/null
+++ b/src/mainboard/facebook/monolith/vboot-rw.fmd
@@ -0,0 +1,28 @@
+FLASH 16M {
+	SI_ALL@0x0 0x700000 {
+		SI_DESC@0x0 0x1000
+		UNUSED_1@0x1000 0x2000
+		SI_ME@0x3000 0x6fd000
+	}
+	SI_BIOS@0x700000 0x900000 {
+		MISC_RW@0x0 0x20000 {
+			RW_MRC_CACHE@0x0 0x10000
+			RW_VPD(PRESERVE)@0x010000 0x2000
+			RW_NVRAM(PRESERVE)@0x012000 0x6000
+		}
+		RW_SECTION_A@0x20000 0x860000 {
+			VBLOCK_A@0x0 0x10000
+			RW_FWID_A@0x10000% 0x40
+			FW_MAIN_A(CBFS)@0x10040% 0x84FFC0
+		}
+		WP_RO@0x880000 0x080000 {
+			RO_SECTION@0x0000 0x80000 {
+				FMAP@0x0% 0x800
+				RO_FRID@0x800% 0x40
+				RO_FRID_PAD@0x840% 0x7c0
+				GBB@0x1000 0x4000
+				COREBOOT(CBFS)@0x5000 0x07B000
+			}
+		}
+	}
+}