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review.coreboot.org / coreboot / 7b97289d56e4758b97ea91990418bc03af14ac5c
commit7b97289d56e4758b97ea91990418bc03af14ac5c[log] [tgz]
authorTim Wawrzynczak <twawrzynczak@chromium.org>Fri Mar 12 11:51:31 2021 -0700
committerPatrick Georgi <pgeorgi@google.com>Mon Mar 15 06:03:45 2021 +0000
treee84c94c9cdc31c008144496b2240a0f369159fa3
parent8d11cdc6fa121f7f5c77b49b6e0ea689c62b3da0 [diff]
mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0

This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the brya0 mainboard.

TEST=snippet from dmesg logs shows the correct resources being allocated:
   PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24
   PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20
   PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24
   PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20
   PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24
   PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1 file changed
tree: e84c94c9cdc31c008144496b2240a0f369159fa3
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.