commit 7b508ddecb25d60945f088914f739ee5b3c2c175
author Duncan Laurie <dlaurie@chromium.org> Mon Apr 09 12:30:43 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue May 01 20:04:41 2012 +0200
tree 105871504649f0f1b3a2a0c4490d10b0c8a9ec26
parent 0ff99b70f5c5b6797507d3f152c5d452e1210110

Only send ME Dram Init Done message on Sandybridge

This is done inside the SystemAgent binary on Ivybridge.

Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/northbridge/intel/sandybridge/raminit.c

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index dcf9f63..bbb743f 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -27,6 +27,7 @@
 #include <cbfs.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
 #include "raminit.h"
 #include "pei_data.h"
 #include "sandybridge.h"
@@ -365,7 +366,13 @@
 		version >> 24 , (version >> 16) & 0xff,
 		(version >> 8) & 0xff, version & 0xff);
 
-	intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+	/* Send ME init done for SandyBridge here.  This is done
+	 * inside the SystemAgent binary on IvyBridge. */
+	if (BASE_REV_SNB ==
+	    (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK))
+		intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+	else
+		intel_early_me_status();
 
 	report_memory_config();