tree 610a4ab2da2f74cb4f6be54e2e1d29f98335bd70
parent 88f863cfbb1f3f547cf503b462e29c285e8f1c94
author Cliff Huang <cliff.huang@intel.corp-partner.google.com> 1655829800 -0700
committer Felix Held <felix-coreboot@felixheld.de> 1655919120 +0000

soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRC

MAX_PCIE_CLOCK_SRC is not an user-configurable option.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>