mb/google/volteer: Configure tcss port information for early tcss init
Implement the mainboard_tcss_get_port_info weak function so that the TCSS
muxes can be properly configured to ensure mapping is correct in mux. This
ensures that any devices that are connected during boot are not improperly
configured by the Kernel.
BUG=b:180426950
BRANCH=firmare-volteer-13672.B
TEST= Verified that the SOC code that initialized TCSS muxes to disconnect
mode is executing properly for all TCSS ports and verified that USB3 devices
are no longer downgrading to USB2 speed if connected during boot.
Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 79f50aa..f3724d8 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -16,6 +16,7 @@
select DRIVERS_SOUNDWIRE_ALC5682
select DRIVERS_SOUNDWIRE_MAX98373
select DRIVERS_USB_ACPI
+ select EARLY_TCSS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_SKUID
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index e8b3466..70fa22b 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -10,6 +10,7 @@
#include <gpio.h>
#include <intelblocks/gpio.h>
#include <security/tpm/tss.h>
+#include <soc/early_tcss.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -141,6 +142,63 @@
}
}
+static bool is_correct_port(const struct device *dev, int port)
+{
+ return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port
+ && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops;
+}
+
+static const struct drivers_intel_pmc_mux_conn_config *get_connector_config(
+ const struct device *mux,
+ int port)
+{
+ const struct drivers_intel_pmc_mux_conn_config *config = NULL;
+ DEVTREE_CONST struct device *conn = NULL;
+
+ while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) {
+ if (is_correct_port(conn, port))
+ break;
+ }
+
+ if (conn)
+ config = (const struct drivers_intel_pmc_mux_conn_config *) conn->chip_info;
+
+ return config;
+}
+
+const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports)
+{
+ static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
+ size_t port;
+ const struct device *pmc;
+ const struct device *mux;
+ const struct drivers_intel_pmc_mux_conn_config *mux_config;
+ size_t active_ports = 0;
+
+ pmc = pcidev_path_on_root(PCH_DEVFN_PMC);
+ if (!pmc || !pmc->link_list) {
+ printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__);
+ return NULL;
+ }
+
+ mux = pmc->link_list->children;
+ if (!mux)
+ return NULL;
+
+ for (port = 0; port < MAX_TYPE_C_PORTS; port++) {
+ mux_config = get_connector_config(mux, port);
+ if (mux_config == NULL)
+ continue;
+
+ port_map[active_ports].usb2_port = mux_config->usb2_port_number;
+ port_map[active_ports].usb3_port = mux_config->usb3_port_number;
+ active_ports++;
+ }
+
+ *num_ports = active_ports;
+ return port_map;
+}
+
static void mainboard_chip_init(void *chip_info)
{
const struct pad_config *base_pads;