mb/amd/birman_plus: Add Birman+ board support for Phoenix SOC
1) Initial commit for upstreaming Birmanplus mainboard changes.
2) Add the DXIO descriptors for Birmanplus mainboard.
Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
new file mode 100644
index 0000000..29ad9c0
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_AMD_BIRMANPLUS_COMMON
+ def_bool n
+ select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM
+ select EC_ACPI
+ select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
+ select DRIVERS_PCIE_RTD3_DEVICE
+ select MAINBOARD_HAS_CHROMEOS
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select PCIEXP_COMMON_CLOCK
+ select PCIEXP_L1_SUB_STATE
+ select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
+ select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
+ select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
+
+
+config BOARD_AMD_BIRMANPLUS_PHOENIX
+ select BOARD_AMD_BIRMANPLUS_COMMON
+ select SOC_AMD_PHOENIX_FSP
+
+if BOARD_AMD_BIRMANPLUS_COMMON
+
+config FMDFILE
+ default "src/mainboard/amd/birman_plus/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMANPLUS_PHOENIX
+ default "src/mainboard/amd/birman_plus/board_phoenix.fmd" if BOARD_AMD_BIRMANPLUS_PHOENIX
+
+config MAINBOARD_DIR
+ default "amd/birman_plus" if BOARD_AMD_BIRMANPLUS_PHOENIX
+
+config MAINBOARD_PART_NUMBER
+ default "Birmanplus_Phoenix" if BOARD_AMD_BIRMANPLUS_PHOENIX
+
+config DEVICETREE
+ default "devicetree_phoenix.cb"
+
+config BIRMANPLUS_HAVE_MCHP_FW
+ bool "Have Microchip EC firmware?"
+ default n
+
+config BIRMANPLUS_MCHP_SIG_FILE
+ string "Microchip EC signature file"
+ depends on BIRMAN_HAVE_MCHP_FW
+ default "3rdparty/blobs/mainboard/amd/birman_plus/EC_birmanplus_sig.bin"
+ help
+ The EC sig blob is the first 4kBytes of the firmware image.
+ The first 4 bytes form a pointer (with CRC) to where the EC firmware
+ is located
+
+config AMD_SOC_CONSOLE_UART
+ default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
+
+config BIRMANPLUS_MCHP_FW_FILE
+ string "Microchip EC firmware file"
+ depends on BIRMAN_HAVE_MCHP_FW
+ default "3rdparty/blobs/mainboard/amd/birman_plus/EC_birmanplus.bin"
+ help
+ The EC firmware blob is at the EC_BODY FMAP region of the firmware image.
+
+config VBOOT
+ select VBOOT_NO_BOARD_SUPPORT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_STARTS_IN_BOOTBLOCK
+
+config VBOOT_VBNV_OFFSET
+ hex
+ default 0x2A
+
+config RO_REGION_ONLY
+ string
+ depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
+ # Add the EFS and EC to the RO region only
+ # This is a birman-specific override of soc/amd/(phoenix | glinda)/Kconfig
+ default "apu/amdfw apu/ecfw"
+
+config CHROMEOS
+ # Use default libpayload config
+ select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
+ # We don't have recovery buttons, so we can't manually enable devmode.
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+
+config ENABLE_EVAL_CARD
+ bool "Enable Eval Card"
+ help
+ Enable the Eval Card PCIe slot
+
+config ENABLE_EVAL_19V
+ bool "Enable 19V rail for Eval Card"
+ depends on ENABLE_EVAL_CARD
+ help
+ Enable the 19V rail for Eval Card PCIe slot
+
+choice
+ prompt "DT SLOT/M.2 SSD1 ENABLE"
+ default ENABLE_DT_SLOT_BIRMANPLUS
+ help
+ Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes.
+
+config ENABLE_DT_SLOT_BIRMANPLUS
+ bool "Enable DT slot"
+
+config ENABLE_M2_SSD1_BIRMANPLUS
+ bool "Enable M.2 SSD1"
+
+config DISABLE_DT_M2_BIRMANPLUS
+ bool "Disable both DT and M.2 slot"
+
+endchoice
+
+choice
+ prompt "WLAN/WWAN Selection"
+ default WLAN0_WWAN0_BIRMANPLUS
+ help
+ WLAN and WWAN lane configuration
+
+config WLAN0_WWAN0_BIRMANPLUS
+ bool "Both WLAN and WWAN Enabled (1 lane each)"
+
+config WLAN01_BIRMANPLUS
+ bool "Only WLAN Enabled (2 lanes WLAN, 0 lanes WWAN)"
+
+config WWAN01_BIRMANPLUS
+ bool "Only WWAN Enabled (2 lanes WWAN, 0 lanes WLAN)"
+
+endchoice
+if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
+config EFS_SPI_READ_MODE
+ default 3 # Quad IO (1-1-4)
+
+config EFS_SPI_SPEED
+ default 0 # 66MHz
+
+config EFS_SPI_MICRON_FLAG
+ default 0
+
+config NORMAL_READ_SPI_SPEED
+ default 1 # 33MHz
+
+config ALT_SPI_SPEED
+ default 1 # 33MHz
+
+config TPM_SPI_SPEED
+ default 1 # 33MHz
+
+endif # !EM100
+
+endif # BOARD_AMD_BIRMANPLUS_COMMON
diff --git a/src/mainboard/amd/birman_plus/Kconfig.name b/src/mainboard/amd/birman_plus/Kconfig.name
new file mode 100644
index 0000000..69834bc
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/Kconfig.name
@@ -0,0 +1,4 @@
+comment "BirmanPlus"
+
+config BOARD_AMD_BIRMANPLUS_PHOENIX
+ bool "-> BirmanPlus for Phoenix SoC"
diff --git a/src/mainboard/amd/birman_plus/Makefile.mk b/src/mainboard/amd/birman_plus/Makefile.mk
new file mode 100644
index 0000000..f08f305
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/Makefile.mk
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors.c
+
+ramstage-y += chromeos.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors.c
+
+
+ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin),)
+APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin
+APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5_DefaultRecovery.bin
+else
+show_notices:: warn_no_apcb
+endif
+
+ifeq ($(CONFIG_BIRMANPLUS_HAVE_MCHP_FW),y)
+$(call add_intermediate, add_mchp_fw)
+ $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_BIRMANPLUS_MCHP_SIG_FILE) --fill-upward
+ $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMANPLUS_MCHP_FW_FILE) --fill-upward
+
+else
+show_notices:: warn_no_mchp
+endif # CONFIG_BIRMAN_HAVE_MCHP_FW
+
+PHONY+=warn_no_mchp
+warn_no_mchp:
+ printf "\n\t** WARNING **\n"
+ printf "coreboot has been built without the EC FW.\n"
+ printf "Do not flash this image. Your Birman's power button\n"
+ printf "will not respond when you press it.\n\n"
diff --git a/src/mainboard/amd/birman_plus/board_info.txt b/src/mainboard/amd/birman_plus/board_info.txt
new file mode 100644
index 0000000..b351b8e
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/board_info.txt
@@ -0,0 +1 @@
+Category: eval
diff --git a/src/mainboard/amd/birman_plus/board_phoenix.fmd b/src/mainboard/amd/birman_plus/board_phoenix.fmd
new file mode 100644
index 0000000..bc09fe7
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/board_phoenix.fmd
@@ -0,0 +1,9 @@
+FLASH@0xFF000000 16M {
+ BIOS {
+ EC_SIG 4K
+ FMAP 4K
+ COREBOOT(CBFS)
+ EC_BODY@15872K 256K
+ RW_MRC_CACHE 256K
+ }
+}
diff --git a/src/mainboard/amd/birman_plus/bootblock.c b/src/mainboard/amd/birman_plus/bootblock.c
new file mode 100644
index 0000000..1c47e6d
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/bootblock.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/espi.h>
+#include "ec.h"
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+ mainboard_program_early_gpios();
+
+ espi_switch_to_spi1_pads();
+}
+
+void bootblock_mainboard_init(void)
+{
+ if (!CONFIG(SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD))
+ birman_ec_init();
+}
diff --git a/src/mainboard/amd/birman_plus/chromeos.c b/src/mainboard/amd/birman_plus/chromeos.c
new file mode 100644
index 0000000..515da94
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/chromeos.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {};
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ /* Birman doesn't have a write protect pin */
+ return 0;
+}
+
+DECLARE_NO_CROS_GPIOS();
diff --git a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
new file mode 100644
index 0000000..9d6d402
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
@@ -0,0 +1,35 @@
+FLASH@0xFF000000 16M {
+ SI_BIOS {
+ WP_RO 8M {
+ EC_SIG 4K
+ RO_VPD(PRESERVE) 16K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ COREBOOT(CBFS)
+ GBB 448K
+ }
+ }
+ RW_SECTION_A 3M {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 256
+ }
+ RW_SECTION_B 3M {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 256
+ }
+ RW_ELOG(PRESERVE) 4K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 20K
+ SMMSTORE(PRESERVE) 64K
+ RW_LEGACY(CBFS)
+ EC_BODY@15872K 256K
+ RW_MRC_CACHE(PRESERVE) 256K
+ }
+}
diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb
new file mode 100644
index 0000000..3fc1f0d
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb
@@ -0,0 +1,291 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# TODO: Update for birman
+
+chip soc/amd/phoenix
+ register "common_config.espi_config" = "{
+ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
+ .generic_io_range[0] = {
+ .base = 0x3f8,
+ .size = 8,
+ },
+ .generic_io_range[1] = {
+ .base = 0x600,
+ .size = 256,
+ },
+ .io_mode = ESPI_IO_MODE_QUAD,
+ .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
+ .crc_check_enable = 1,
+ .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
+ .periph_ch_en = 1,
+ .vw_ch_en = 1,
+ .oob_ch_en = 1,
+ .flash_ch_en = 0,
+ }"
+
+ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+ GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+
+ register "i2c[0].early_init" = "1"
+ register "i2c[1].early_init" = "1"
+ register "i2c[2].early_init" = "1"
+ register "i2c[3].early_init" = "1"
+
+ # I2C Pad Control RX Select Configuration
+ register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
+
+ register "s0ix_enable" = "true"
+
+ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
+
+ register "usb_phy_custom" = "1"
+ register "usb_phy" = "{
+ .Usb2PhyPort[0] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[1] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[2] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[3] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[4] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[5] = {
+ .compdistune = 0x1,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x3,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[6] = {
+ .compdistune = 0x3,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x6,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb2PhyPort[7] = {
+ .compdistune = 0x3,
+ .pllbtune = 0x1,
+ .pllitune = 0x0,
+ .pllptune = 0xc,
+ .sqrxtune = 0x2,
+ .txfslstune = 0x1,
+ .txpreempamptune = 0x3,
+ .txpreemppulsetune = 0x0,
+ .txrisetune = 0x1,
+ .txvreftune = 0x6,
+ .txhsxvtune = 0x3,
+ .txrestune = 0x2,
+ },
+ .Usb3PhyPort[0] = {
+ .tx_term_ctrl = 0x2,
+ .rx_term_ctrl = 0x2,
+ .tx_vboost_lvl_en = 0x0,
+ .tx_vboost_lvl = 0x5,
+ },
+ .Usb3PhyPort[1] = {
+ .tx_term_ctrl = 0x2,
+ .rx_term_ctrl = 0x2,
+ .tx_vboost_lvl_en = 0x0,
+ .tx_vboost_lvl = 0x5,
+ },
+ .Usb3PhyPort[2] = {
+ .tx_term_ctrl = 0x2,
+ .rx_term_ctrl = 0x2,
+ .tx_vboost_lvl_en = 0x0,
+ .tx_vboost_lvl = 0x5,
+ },
+ .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
+ .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+ .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
+ .BatteryChargerEnable = 0,
+ .PhyP3CpmP4Support = 0,
+ }"
+
+ register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM
+ register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1
+ register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0
+ register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN
+ register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN
+ register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD
+ register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE
+
+ device domain 0 on
+ device ref iommu on end
+ device ref gpp_bridge_1_1 on end # MXM
+ device ref gpp_bridge_1_2 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVMe SSD1
+ device ref gpp_bridge_1_3 on end # GBE
+ device ref gpp_bridge_2_1 on end # SD
+ device ref gpp_bridge_2_2 on end # WWAN
+ device ref gpp_bridge_2_3 on end # WIFI
+ device ref gpp_bridge_2_4 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVMe SSD0
+ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
+ device ref gfx on end # Internal GPU (GFX)
+ device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
+ device ref crypto on end # Crypto Coprocessor
+ device ref xhci_0 on # USB 3.1 (USB0)
+ chip drivers/usb/acpi
+ device ref xhci_0_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port6 on end
+ end
+ end
+ end
+ end
+ device ref xhci_1 on # USB 3.1 (USB1)
+ chip drivers/usb/acpi
+ device ref xhci_1_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port7 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port7 on end
+ end
+ end
+ end
+ end
+ device ref acp on end # Audio Processor (ACP)
+ end
+ device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
+ device ref usb4_xhci_0 on
+ chip drivers/usb/acpi
+ device ref usb4_xhci_0_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port0 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port0 on end
+ end
+ end
+ end
+ end
+ device ref usb4_xhci_1 on
+ chip drivers/usb/acpi
+ device ref usb4_xhci_1_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port1 on end
+ end
+ end
+ end
+ end
+ end
+ end
+
+ device ref i2c_0 on end
+ device ref i2c_1 on end
+ device ref i2c_2 on end
+ device ref i2c_3 on end
+ device ref uart_0 on end # UART0
+
+end
diff --git a/src/mainboard/amd/birman_plus/dsdt.asl b/src/mainboard/amd/birman_plus/dsdt.asl
new file mode 100644
index 0000000..7b8982a
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/dsdt.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock (
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{
+ #include <acpi/dsdt_top.asl>
+
+ #include <soc.asl>
+}
diff --git a/src/mainboard/amd/birman_plus/early_gpio.c b/src/mainboard/amd/birman_plus/early_gpio.c
new file mode 100644
index 0000000..4915996
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/early_gpio.c
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include "gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+ /* TPM CS */
+ PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE),
+ /* ESPI_CS_L */
+ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+ /* ESPI_SOC_CLK */
+ PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
+ /* ESPI_DATA0 */
+ PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
+ /* ESPI_DATA1 */
+ PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
+ /* ESPI_DATA2 */
+ PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
+ /* ESPI_DATA3 */
+ PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
+ /* ESPI_ALERT_L */
+ PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
+ /* TPM IRQ */
+ PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+ /* SPI_ROM_REQ */
+ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
+ /* SPI_ROM_GNT */
+ PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE),
+ /* KBRST_L */
+ PAD_NF(GPIO_21, KBRST_L, PULL_NONE),
+
+ /* Deassert PCIe Reset lines */
+ /* PCIE_RST0_L */
+ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
+ /* PCIE_RST1_L */
+ PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
+ /* M2_SSD0_RST_L */
+ PAD_GPO(GPIO_78, HIGH),
+ /* M2_SSD1_RST_L */
+ PAD_GPO(GPIO_79, HIGH),
+
+ /* Enable UART 2 */
+ /* UART2_RXD */
+ PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
+ /* UART2_TXD */
+ PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
+ /* Enable UART 0 */
+ /* UART0_RXD */
+ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
+ /* UART0_TXD */
+ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
+ /* FANOUT0 */
+ PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
+
+ /* I2C0 SCL */
+ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
+ /* I2C0 SDA */
+ PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
+ /* I2C1 SCL */
+ PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
+ /* I2C1 SDA */
+ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
+ /* I2C2_SCL */
+ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
+ /* I2C2_SDA */
+ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
+ /* I2C3_SCL */
+ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+ /* I2C3_SDA */
+ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
+};
+
+void mainboard_program_early_gpios(void)
+{
+ gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}
diff --git a/src/mainboard/amd/birman_plus/ec.c b/src/mainboard/amd/birman_plus/ec.c
new file mode 100644
index 0000000..2ddc049
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/ec.c
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <ec/acpi/ec.h>
+#include <stdint.h>
+#include "ec.h"
+
+#define BIRMAN_EC_CMD 0x666
+#define BIRMAN_EC_DATA 0x662
+
+#define EC_GPIO_1_ADDR 0xA1
+#define EC1_EVAL_PWREN BIT(1)
+
+#define EC_GPIO_2_ADDR 0xA2
+#define EC2_EVAL_SLOT_PWREN BIT(5)
+#define EC2_EVAL_19V_EN BIT(2)
+
+#define EC_GPIO_3_ADDR 0xA3
+#define EC3_WLAN_RST_AUX BIT(5)
+#define EC3_WWAN_RST_AUX BIT(4)
+#define EC3_SD_RST_AUX BIT(3)
+#define EC3_DT_RST_AUX BIT(2)
+#define EC3_LOM_RST_AUX BIT(1)
+#define EC3_EVAL_RST_AUX BIT(0)
+
+#define EC_GPIO_7_ADDR 0xA7
+#define EC7_WWAN_PWR_OFF_N BIT(7)
+#define EC7_BT_RADIO_DIS BIT(2)
+#define EC7_WL_RADIO_DIS BIT(0)
+
+#define EC_GPIO_8_ADDR 0xA8
+#define EC8_ADAPTER_OFF BIT(5)
+#define EC8_EVAL_SMBUS1_N_SW BIT(3)
+#define EC8_MP2_SEL BIT(2)
+#define EC8_DT_N_SSD1_SW BIT(1)
+
+#define EC_GPIO_9_ADDR 0xA9
+#define EC9_CAM0_PWR_EN BIT(7)
+#define EC9_CAM1_PWR_EN BIT(6)
+#define EC9_WWAN_RST BIT(5)
+#define EC9_DT_PWREN BIT(2)
+#define EC9_TPM_PWR_EN BIT(1)
+#define EC9_TPM_S0I3_N BIT(0)
+
+#define EC_GPIO_A_ADDR 0xAA
+#define ECA_MUX2_S0 BIT(7)
+#define ECA_MUX2_S1 BIT(6)
+#define ECA_MUX1_S0 BIT(5)
+#define ECA_MUX1_S1 BIT(4)
+#define ECA_MUX0_S0 BIT(3)
+#define ECA_MUX0_S1 BIT(2)
+#define ECA_SMBUS1_EN BIT(1)
+#define ECA_SMBUS0_EN BIT(0)
+
+#define EC_GPIO_C_ADDR 0xAC
+#define ECC_TPNL_BUF_EN BIT(6)
+#define ECC_TPAD_BUF_EN BIT(5)
+#define ECC_NFC_BUF_EN BIT(4)
+
+#define EC_GPIO_D_ADDR 0xAD
+#define ECD_TPNL_PWR_EN BIT(7)
+#define ECD_TPNL_EN BIT(6)
+#define ECD_SSD1_PWR_EN BIT(5)
+#define ECD_FPR_PWR_EN BIT(3)
+#define ECD_FPR_OFF_N BIT(2)
+#define ECD_FPR_LOCK_N BIT(1)
+#define ECD_TPAD_DISABLE_N BIT(0)
+
+#define EC_GPIO_E_ADDR 0xAE
+#define ECE_LOM_PWR_EN BIT(7)
+#define ECE_SSD0_PWR_EN BIT(6)
+#define ECE_SD_PWR_EN BIT(5)
+#define ECE_WLAN_PWR_EN BIT(4)
+#define ECE_WWAN_PWR_EN BIT(3)
+#define ECE_CAM_PWR_EN BIT(2)
+#define ECE_FPR_N_GBE_SEL BIT(1)
+#define ECE_BT_N_TPNL_SEL BIT(0)
+
+#define EC_GPIO_F_ADDR 0xAF
+#define ECF_CAM_FW_WP_N BIT(7)
+#define ECF_I2C_MUX_OE_N BIT(4)
+#define ECF_WLAN0_N_WWAN1_SW BIT(1)
+#define ECF_WWAN0_N_WLAN1_SW BIT(0)
+
+#define EC_GPIO_G_ADDR 0xB0
+#define ECG_IR_LED_PWR_EN BIT(7)
+#define ECG_U0_WLAN_HDR_SEL BIT(6)
+#define ECG_DT_SSD1_MUX_OFF BIT(5)
+#define ECG_WLAN_WWAN_MUX_OFF BIT(4)
+
+static void configure_ec_gpio(void)
+{
+ uint8_t tmp;
+
+ tmp = ec_read(EC_GPIO_1_ADDR);
+ if (CONFIG(ENABLE_EVAL_CARD)) {
+ tmp |= EC1_EVAL_PWREN;
+ } else {
+ tmp &= ~EC1_EVAL_PWREN;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_1_ADDR, tmp);
+ ec_write(EC_GPIO_1_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_2_ADDR);
+ if (CONFIG(ENABLE_EVAL_CARD)) {
+ tmp |= EC2_EVAL_SLOT_PWREN;
+ if (CONFIG(ENABLE_EVAL_19V)) {
+ tmp |= EC2_EVAL_19V_EN;
+ } else {
+ tmp &= ~EC2_EVAL_19V_EN;
+ }
+ } else {
+ tmp &= ~EC2_EVAL_SLOT_PWREN;
+ tmp &= ~EC2_EVAL_19V_EN;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp);
+ ec_write(EC_GPIO_2_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_3_ADDR);
+ tmp |= EC3_WLAN_RST_AUX | EC3_WWAN_RST_AUX | EC3_SD_RST_AUX;
+ tmp |= EC3_DT_RST_AUX | EC3_LOM_RST_AUX | EC3_EVAL_RST_AUX;
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp);
+ ec_write(EC_GPIO_3_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_7_ADDR);
+ tmp &= ~EC7_BT_RADIO_DIS;
+ tmp &= ~EC7_WL_RADIO_DIS;
+ tmp |= EC7_WWAN_PWR_OFF_N;
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
+ ec_write(EC_GPIO_7_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_8_ADDR);
+ if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) {
+ tmp |= EC8_DT_N_SSD1_SW;
+ } else {
+ tmp &= ~EC8_DT_N_SSD1_SW;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
+ ec_write(EC_GPIO_8_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_9_ADDR);
+ tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN;
+ if (CONFIG(ENABLE_DT_SLOT_BIRMANPLUS)) {
+ tmp |= EC9_DT_PWREN;
+ } else {
+ tmp &= ~EC9_DT_PWREN;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp);
+ ec_write(EC_GPIO_9_ADDR, tmp);
+
+ tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN;
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_A_ADDR, tmp);
+ ec_write(EC_GPIO_A_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_C_ADDR);
+ tmp |= ECC_TPNL_BUF_EN | ECC_TPAD_BUF_EN | ECC_NFC_BUF_EN;
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_C_ADDR, tmp);
+ ec_write(EC_GPIO_C_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_D_ADDR);
+ tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N;
+ if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) {
+ tmp |= ECD_SSD1_PWR_EN;
+ } else {
+ tmp &= ~ECD_SSD1_PWR_EN;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp);
+ ec_write(EC_GPIO_D_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_E_ADDR);
+ tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN;
+ tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL;
+ tmp &= ~ECE_BT_N_TPNL_SEL;
+ if (CONFIG(WLAN01_BIRMANPLUS)) { // no WWAN, turn off WWAN power
+ tmp &= ~ECE_WWAN_PWR_EN;
+ } else {
+ tmp |= ECE_WWAN_PWR_EN;
+ }
+ if (CONFIG(WWAN01_BIRMANPLUS)) { // no WLAN, turn off WLAN power
+ tmp &= ~ECE_WLAN_PWR_EN;
+ } else {
+ tmp |= ECE_WLAN_PWR_EN;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_E_ADDR, tmp);
+ ec_write(EC_GPIO_E_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_F_ADDR);
+ if (CONFIG(WLAN01_BIRMANPLUS)) {
+ tmp |= ECF_WWAN0_N_WLAN1_SW;
+ } else {
+ tmp &= ~ECF_WWAN0_N_WLAN1_SW;
+ }
+ if (CONFIG(WWAN01_BIRMANPLUS)) {
+ tmp |= ECF_WLAN0_N_WWAN1_SW;
+ } else {
+ tmp &= ~ECF_WLAN0_N_WWAN1_SW;
+ }
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_F_ADDR, tmp);
+ ec_write(EC_GPIO_F_ADDR, tmp);
+
+ tmp = ec_read(EC_GPIO_G_ADDR);
+ tmp &= ~ECG_DT_SSD1_MUX_OFF;
+ tmp &= ~ECG_WLAN_WWAN_MUX_OFF;
+ tmp |= ECG_IR_LED_PWR_EN | ECG_U0_WLAN_HDR_SEL;
+ printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_G_ADDR, tmp);
+ ec_write(EC_GPIO_G_ADDR, tmp);
+}
+
+void birman_ec_init(void)
+{
+ ec_set_ports(BIRMAN_EC_CMD, BIRMAN_EC_DATA);
+ configure_ec_gpio();
+}
diff --git a/src/mainboard/amd/birman_plus/ec.h b/src/mainboard/amd/birman_plus/ec.h
new file mode 100644
index 0000000..d8e54db
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BIRMAN_EC_H
+#define BIRMAN_EC_H
+
+void birman_ec_init(void);
+
+#endif /* BIRMAN_EC_H */
diff --git a/src/mainboard/amd/birman_plus/gpio.c b/src/mainboard/amd/birman_plus/gpio.c
new file mode 100644
index 0000000..74d929d
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/gpio.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include "gpio.h"
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+ /* PWR_BTN_L */
+ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
+ /* SYS_RESET_L */
+ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
+ /* WAKE_L */
+ PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
+ /* PCIE_SD_WAKE_L */
+ PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW),
+ /* UART_WAKE_L_M2_APU */
+ PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW),
+ /* MPM_EVENT_L, input or OD output */
+ PAD_GPI(GPIO_5, PULL_UP),
+ /* TPNL_INT_L */
+ PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW),
+ /* EC SCI */
+ PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW),
+ /* TPAD_INT_L */
+ PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW),
+ /* SD_CARD_PRSNT_L */
+ PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */
+ /* VDD_MEM_VID0 */
+ PAD_GPO(GPIO_10, HIGH),
+ /* HP_MIC_DET_L */
+ PAD_GPI(GPIO_11, PULL_UP),
+ /* ALIGN_FLAG_MU_L */
+ PAD_GPO(GPIO_12, HIGH),
+ /* GPIO_13 - GPIO_15: Not available */
+ /* USB_OC0_L */
+ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
+ /* WAKE_ON_WAN_L */
+ PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW),
+ /* PCIE_WLAN_WAKE_L */
+ PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW),
+ /* I2C3_SCL */
+ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+ /* I2C3_SDA */
+ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
+ /* KBRST_L */
+ PAD_NF(GPIO_21, KBRST_L, PULL_NONE),
+ /* ESPI_ALERT_L */
+ PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
+ /* AC_PRES */
+ PAD_NF(GPIO_23, AC_PRES, PULL_NONE),
+ /* PCIE_LOM_WAKE_L */
+ PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+ /* GPIO_25: Not available */
+ /* PCIE_RST0_L */
+ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
+ /* PCIE_RST1_L */
+ PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
+ /* GPIO_28: Not available */
+ /* TPM CS */
+ PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE),
+ /* ESPI_CS_L */
+ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+ /* INT_CLKREQ_L */
+ PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+ /* LPC_RST_L */
+ PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE),
+ /* GPIO_33 - GPIO_37: Not available */
+ /* CLK_REQ5_L */
+ PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE),
+ /* CLK_REQ6_L */
+ PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE),
+ /* USB2_HDR_P0/1_SMI */
+ PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW),
+ /* GPIO_41: Not available */
+ /* VDD_MEM_VID1 */
+ PAD_GPO(GPIO_42, HIGH),
+ /* GPIO_43 - GPIO_66: Not available */
+ /* SPI_ROM_REQ */
+ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
+ /* ESPI_DATA2 */
+ PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
+ /* ESPI_DATA3 */
+ PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
+ /* SPI2_CLK */
+ PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE),
+ /* GPIO_71 - GPIO_73: Not available */
+ /* APU_NFC_DWL_REQ_1V8 */
+ PAD_GPO(GPIO_74, LOW),
+ /* SPI2_CS1_L */
+ PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE),
+ /* SPI_ROM_GNT */
+ PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE),
+ /* ESPI_SOC_CLK */
+ PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
+ /* M2_SSD0_RST_L */
+ PAD_GPO(GPIO_78, HIGH),
+ /* M2_SSD1_RST_L */
+ PAD_GPO(GPIO_79, HIGH),
+ /* ESPI_DATA1 */
+ PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
+ /* ESPI_DATA0 */
+ PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
+ /* GPIO_82 - GPIO_83: Not available */
+ /* FANIN0 */
+ PAD_NF(GPIO_84, FANIN0, PULL_NONE),
+ /* FANOUT0 */
+ PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
+ /* GPIO_86 - GPIO_88: Not available */
+ /* I2S CODEC INT */
+ PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW),
+ /* ALERT_L_M2_SSD0 */
+ PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW),
+ /* NFC IRQ */
+ PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW),
+ /* CLK_REQ0_L */
+ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
+ /* GPIO_93 - GPIO_103: Not available */
+ /* SPI2_DAT0 */
+ PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE),
+ /* SPI2_DAT1 */
+ PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE),
+ /* SPI2_DAT2 */
+ PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE),
+ /* SPI2_DAT3 */
+ PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE),
+ /* GPIO_108 - GPIO_112: Not available */
+ /* I2C2_SCL */
+ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
+ /* I2C2_SDA */
+ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
+ /* CLK_REQ1_L */
+ PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
+ /* CLK_REQ2_L */
+ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
+ /* GPIO_117 - GPIO_129: Not available */
+ /* TPM IRQ */
+ PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+ /* CLK_REQ3_L */
+ PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE),
+ /* CLK_REQ4_L */
+ PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE),
+ /* GPIO_133 - GPIO_134: Not available */
+ /* UART2_CTS_L */
+ PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE),
+ /* UART2_RXD */
+ PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
+ /* UART2_RTS_L */
+ PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE),
+ /* UART2_TXD */
+ PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
+ /* M2_SSD2_RST_L */
+ PAD_GPO(GPIO_139, HIGH),
+ /* UART0_CTS_L */
+ PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE),
+ /* UART0_RXD */
+ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
+ /* UART0_RTS_L */
+ PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE),
+ /* UART0_TXD */
+ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
+ /* M2_SSD3_RST_L */
+ PAD_GPO(GPIO_144, HIGH),
+ /* I2C0 SCL */
+ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
+ /* I2C0 SDA */
+ PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
+ /* I2C1 SCL */
+ PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
+ /* I2C1 SDA */
+ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
+ /* GPIO_149 - GPIO_152: Not available */
+ /* UART4_CTS_L */
+ PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE),
+ /* UART4_RTS_L */
+ PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE),
+ /* UART4_RXD */
+ PAD_NF(GPIO_155, UART4_RXD, PULL_NONE),
+ /* UART4_TXD */
+ PAD_NF(GPIO_156, UART4_TXD, PULL_NONE),
+ /* M2_SSD4_RST_L */
+ PAD_GPO(GPIO_157, HIGH),
+};
+
+void mainboard_program_gpios(void)
+{
+ gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+}
diff --git a/src/mainboard/amd/birman_plus/gpio.h b/src/mainboard/amd/birman_plus/gpio.h
new file mode 100644
index 0000000..04c98c5
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
+void mainboard_program_gpios(void); /* ramstage GPIO configuration */
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/amd/birman_plus/mainboard.c b/src/mainboard/amd/birman_plus/mainboard.c
new file mode 100644
index 0000000..0deba67
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/mainboard.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/amd_pci_util.h>
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <types.h>
+#include "gpio.h"
+
+/* TODO: Update for birman */
+
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ * 0: timer < soc/amd/common/acpi/lpc.asl
+ * 1: i8042 - Keyboard
+ * 2: cascade
+ * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ * 9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing fch_irq_map[] = {
+ { PIRQ_A, 12, PIRQ_NC },
+ { PIRQ_B, 14, PIRQ_NC },
+ { PIRQ_C, 15, PIRQ_NC },
+ { PIRQ_D, 12, PIRQ_NC },
+ { PIRQ_E, 14, PIRQ_NC },
+ { PIRQ_F, 15, PIRQ_NC },
+ { PIRQ_G, 12, PIRQ_NC },
+ { PIRQ_H, 14, PIRQ_NC },
+
+ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
+ { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
+ { PIRQ_GPIO, 11, 11 },
+ { PIRQ_I2C0, 10, 10 },
+ { PIRQ_I2C1, 7, 7 },
+ { PIRQ_I2C2, 6, 6 },
+ { PIRQ_I2C3, 5, 5 },
+ { PIRQ_UART0, 4, 4 },
+ { PIRQ_UART1, 3, 3 },
+
+ /* The MISC registers are not interrupt numbers */
+ { PIRQ_MISC, 0xfa, 0x00 },
+ { PIRQ_MISC0, 0x91, 0x00 },
+ { PIRQ_HPET_L, 0x00, 0x00 },
+ { PIRQ_HPET_H, 0x00, 0x00 },
+};
+
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+{
+ *length = ARRAY_SIZE(fch_irq_map);
+ return fch_irq_map;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ mainboard_program_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+};
diff --git a/src/mainboard/amd/birman_plus/port_descriptors.c b/src/mainboard/amd/birman_plus/port_descriptors.c
new file mode 100644
index 0000000..85f448e
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/port_descriptors.c
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/i2c_simple.h>
+#include <gpio.h>
+#include <soc/platform_descriptors.h>
+#include <soc/soc_util.h>
+#include <types.h>
+
+#define phx_mxm_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = CONFIG(ENABLE_EVAL_CARD), \
+ .start_lane = 0, \
+ .end_lane = 7, \
+ .device_number = 1, \
+ .function_number = 1, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ0, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+#define ssd0_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = true, \
+ .start_lane = 16, \
+ .end_lane = 19, \
+ .device_number = 2, \
+ .function_number = 4, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ2, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+#define wlan_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = true, \
+ .start_lane = 15, \
+ .end_lane = 15, \
+ .device_number = 2, \
+ .function_number = 2, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ3, \
+}
+
+#define phx_ssd1_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = true, \
+ .start_lane = 8, \
+ .end_lane = 11, \
+ .device_number = 1, \
+ .function_number = 2, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ1, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+#define wwan_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = true, \
+ .start_lane = 12, \
+ .end_lane = 12, \
+ .device_number = 2, \
+ .function_number = 3, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ4, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+#define gbe_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = true, \
+ .start_lane = 13, \
+ .end_lane = 13, \
+ .device_number = 1, \
+ .function_number = 3, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ6, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+#define sd_dxio_descriptor { \
+ .engine_type = PCIE_ENGINE, \
+ .port_present = false, \
+ .start_lane = 14, \
+ .end_lane = 14, \
+ .device_number = 2, \
+ .function_number = 1, \
+ .link_speed_capability = GEN_MAX, \
+ .turn_off_unused_lanes = true, \
+ .link_aspm = ASPM_L1, \
+ .link_hotplug = HOTPLUG_DISABLED, \
+ .clk_req = CLK_REQ5, \
+ .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \
+}
+
+static fsp_ddi_descriptor birmanplus_ddi_descriptors[] = {
+ { /* DDI0 - eDP */
+ .connector_type = DDI_EDP,
+ .aux_index = DDI_AUX1,
+ .hdp_index = DDI_HDP1
+ },
+ { /* DDI1 - HDMI/DP */
+ .connector_type = DDI_HDMI,
+ .aux_index = DDI_AUX2,
+ .hdp_index = DDI_HDP2
+ },
+ { /* DDI2 - DP (type C) */
+ .connector_type = DDI_DP_W_TYPEC,
+ .aux_index = DDI_AUX3,
+ .hdp_index = DDI_HDP3,
+ },
+ { /* DDI3 - DP (type C) */
+ .connector_type = DDI_DP_W_TYPEC,
+ .aux_index = DDI_AUX4,
+ .hdp_index = DDI_HDP4,
+ },
+ { /* DDI4 - DP (type C) */
+ .connector_type = DDI_DP_W_TYPEC,
+ .aux_index = DDI_AUX5,
+ .hdp_index = DDI_HDP5,
+ }
+};
+
+static uint8_t get_ddi1_type(void)
+{
+ const uint8_t eeprom_i2c_bus = 2;
+ const uint8_t eeprom_i2c_address = 0x55;
+ const uint16_t eeprom_connector_type_offset = 2;
+ uint8_t eeprom_connector_type_data[2];
+ uint16_t connector_type;
+
+ if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
+ eeprom_connector_type_offset, eeprom_connector_type_data,
+ sizeof(eeprom_connector_type_data))) {
+ printk(BIOS_NOTICE,
+ "Display connector type couldn't be determined. Disabling DDI1.\n");
+ return DDI_UNUSED_TYPE;
+ }
+
+ connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
+
+ switch (connector_type) {
+ case 0x0c:
+ printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
+ return DDI_HDMI;
+ case 0x13:
+ printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
+ return DDI_DP;
+ case 0x14:
+ printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
+ return DDI_EDP;
+ case 0x17:
+ printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n");
+ return DDI_DP_W_TYPEC;
+ default:
+ printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
+ connector_type);
+ return DDI_UNUSED_TYPE;
+ }
+}
+
+
+void mainboard_get_dxio_ddi_descriptors(
+ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+ const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+ birmanplus_ddi_descriptors[1].connector_type = get_ddi1_type();
+
+ printk(BIOS_DEBUG, "Using Birmanplus PHX DXIO\n");
+ static const fsp_dxio_descriptor birmanplus_phx_dxio_descriptors[] = {
+ phx_mxm_dxio_descriptor,
+ ssd0_dxio_descriptor,
+ wlan_dxio_descriptor,
+ phx_ssd1_dxio_descriptor,
+ wwan_dxio_descriptor,
+ gbe_dxio_descriptor,
+ sd_dxio_descriptor,
+ };
+
+ *dxio_descs = birmanplus_phx_dxio_descriptors;
+ *dxio_num = ARRAY_SIZE(birmanplus_phx_dxio_descriptors);
+ *ddi_descs = birmanplus_ddi_descriptors;
+ *ddi_num = ARRAY_SIZE(birmanplus_ddi_descriptors);
+}