soc/amd/cezanne: add MP init and SMM initialization
Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 98c3484..7a2c2d0 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -22,6 +22,8 @@
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select IOAPIC
+ select PARALLEL_MP
+ select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select RESET_VECTOR_IN_RAM
select RTC
@@ -46,6 +48,7 @@
select SSE2
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS
+ select X86_AMD_INIT_SIPI
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 5568
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 2ec41a5..6754bba 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,15 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h>
+#include <amdblocks/smm.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <device/device.h>
#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/reset.h>
+
+/* MP and SMM loading initialization */
+
+/*
+ * Do essential initialization tasks before APs can be fired up -
+ *
+ * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
+ * creates the MTRR solution that the APs will use. Otherwise APs will try to
+ * apply the incomplete solution as the BSP is calculating it.
+ */
+static void pre_mp_init(void)
+{
+ x86_setup_mtrrs_with_detect_no_above_4gb();
+ x86_mtrr_check();
+}
+
+static void post_mp_init(void)
+{
+ global_smi_enable();
+ apm_control(APM_CNT_SMMINFO);
+}
+
+static const struct mp_ops mp_ops = {
+ .pre_mp_init = pre_mp_init,
+ .get_cpu_count = get_cpu_count,
+ .get_smm_info = get_smm_info,
+ .relocation_handler = smm_relocation_handler,
+ .post_mp_init = post_mp_init,
+};
void mp_init_cpus(struct bus *cpu_bus)
{
+ /* Clear for take-off */
+ if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
+ printk(BIOS_ERR, "MP initialization failure.\n");
+
+ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+ set_warm_reset_flag();
}
static void zen_2_3_init(struct device *dev)