intel/dcp847ske: Add Intel NUC DCP847SKE
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE
Created using autoport and manual edits.
mainboard_fill_pei_data copied and adjusted from samsung/lumpy.
Tested:
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V).
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V).
- SeaBIOS stable payload.
- Linux 4.13.14 payload.
- Booting into Linux 4.13.14 with Debian/unstable installed on the
internal mSATA slot.
- Non-native raminit (works).
- Native raminit
- KVR1333D3S9 doesn't work.
- KVR16LS11 only works at 1.5V.
- Native VGA init, HDMI port detection with libgfxinit.
- Basic ACPI functions (power button event; power-off; reboot).
- Suspend to RAM and resume works.
- PCIe WLAN in half-minicard slot.
- USB device in half-minicard slot.
- PCIe device in full-minicard slot.
- mSATA device in full-minicard slot.
- Fan spins up/down in response to CPU load.
Known issues:
- Native raminit fails timC calibration with the RAM I have.
- Technical Product Specification mentions overcurrent protection
for back panel and front panel USB connectors, but I haven't
been able to trigger it with either native fw or coreboot
(tried up to 2.5A load).
Untested:
- USB debug port.
Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig
new file mode 100644
index 0000000..1fd3d8c
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/Kconfig
@@ -0,0 +1,92 @@
+if BOARD_INTEL_DCP847SKE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select CPU_INTEL_SOCKET_RPGA989
+ select SUPERIO_NUVOTON_NCT6776
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select SERIRQ_CONTINUOUS_MODE
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+
+menu "Debugging"
+
+config DISABLE_UART_ON_TESTPADS
+ bool "Disable UART on testpads"
+ default y
+ select NO_UART_ON_SUPERIO
+ help
+ Serial output requires soldering to the testpad next to
+ NCT5577D pin 18 (txd) and gnd.
+
+endmenu
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default intel/dcp847ske
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Intel NUC DCP847SKE"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0106"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x2044
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x8086
+
+config MAX_CPUS
+ int
+ default 2
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config IFD_GBE_SECTION
+ string
+ default "0x00001000:0x00002fff"
+
+config IFD_ME_SECTION
+ string
+ default "0x00003000:0x001bffff"
+
+config IFD_BIOS_SECTION
+ string
+ default "0x001c0000:0x007fffff"
+
+config CBFS_SIZE
+ hex
+ default 0x00640000
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+ string
+ default "Intel Corporation"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+ string
+ default "DCP847SKE"
+
+endif # BOARD_INTEL_DCP847SKE
diff --git a/src/mainboard/intel/dcp847ske/Kconfig.name b/src/mainboard/intel/dcp847ske/Kconfig.name
new file mode 100644
index 0000000..e55b90d
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_DCP847SKE
+ bool "Intel NUC DCP847SKE"
diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc
new file mode 100644
index 0000000..96bac06
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/Makefile.inc
@@ -0,0 +1,4 @@
+romstage-y += early_southbridge.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+smm-y += smihandler.c
diff --git a/src/mainboard/intel/dcp847ske/acpi/ec.asl b/src/mainboard/intel/dcp847ske/acpi/ec.asl
new file mode 100644
index 0000000..09f905e
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/acpi/ec.asl
@@ -0,0 +1 @@
+/* Dummy file required by pch.asl - No license necessary. */
diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/dcp847ske/acpi/platform.asl
new file mode 100644
index 0000000..ff5b176
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/acpi/platform.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl
new file mode 100644
index 0000000..09f905e
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl
@@ -0,0 +1 @@
+/* Dummy file required by pch.asl - No license necessary. */
diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c
new file mode 100644
index 0000000..88c7019
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Enable USB ports in S3 by default */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Enable USB ports in S5 by default */
+ gnvs->s5u0 = 1;
+ gnvs->s5u1 = 1;
+
+ // No LID: open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
diff --git a/src/mainboard/intel/dcp847ske/board_info.txt b/src/mainboard/intel/dcp847ske/board_info.txt
new file mode 100644
index 0000000..32d4eba
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
new file mode 100644
index 0000000..4ff27fd
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -0,0 +1,108 @@
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort 1 Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable DisplayPort 0 Hotplug with 6ms pulse
+ register "gpu_dp_c_hotplug" = "0x06"
+
+ # Enable DVI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_battery" = "1"
+ register "c2_battery" = "3"
+ register "c3_battery" = "5"
+
+ register "c1_acpower" = "1"
+ register "c2_acpower" = "3"
+ register "c3_acpower" = "5"
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on end # Host bridge Host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff
+
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 off end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1 (unused)
+ device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA)
+ device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe)
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6776
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.1 off end # Parallel port
+ device pnp 4e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.3 off end # COM2, IR
+ device pnp 4e.5 off end # Keyboard
+ device pnp 4e.6 off end # CIR
+ device pnp 4e.7 on end # GPIO6
+ device pnp 4e.107 on end # GPIO7
+ device pnp 4e.207 off end # GPIO8
+ device pnp 4e.307 off end # GPIO9
+ device pnp 4e.8 off end # WDT
+ device pnp 4e.108 on end # GPIO0
+ device pnp 4e.208 off end # GPIOA
+ device pnp 4e.308 on # GPIOBASE
+ io 0x60 = 0xa80
+ end
+ device pnp 4e.109 off end # GPIO1
+ device pnp 4e.209 on end # GPIO2
+ device pnp 4e.309 off end # GPIO3
+ device pnp 4e.409 off end # GPIO4
+ device pnp 4e.509 off end # GPIO5
+ device pnp 4e.609 off end # GPIO6
+ device pnp 4e.709 off end # GPIO7
+ device pnp 4e.a on end # ACPI
+ device pnp 4e.b on # HWM, front pannel LED
+ io 0x60 = 0xa30
+ io 0x62 = 0 # unused
+ end
+ device pnp 4e.d off end # VID
+ device pnp 4e.e off end # CIR WAKE-UP
+ device pnp 4e.f off end # GPIO
+ device pnp 4e.14 off end # SVID
+ device pnp 4e.16 off end # Deep sleep
+ device pnp 4e.17 off end # GPIOA
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl
new file mode 100644
index 0000000..f637648
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+ }
+ }
+}
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
new file mode 100644
index 0000000..b15f11f
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <halt.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/raminit_native.h"
+
+#include "superio.h"
+#include "thermal.h"
+
+#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#define DEBUG_UART_EN 0
+#else
+#define DEBUG_UART_EN COMA_LPC_EN
+#endif
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF2_LPC_EN | DEBUG_UART_EN);
+ /* Decode SuperIO 0x0a00 */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
+}
+
+void rcba_config(void)
+{
+ /* Disable devices */
+ RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
+
+#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+ /* Enable Gigabit Ethernet */
+ if (RCBA32(BUC) & PCH_DISABLE_GBE) {
+ RCBA32(BUC) &= ~PCH_DISABLE_GBE;
+ /* Datasheet says clearing the bit requires a reset after */
+ printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
+ outb(0xe, 0xcf9);
+ halt();
+ }
+#endif
+
+ /* Set "mobile" bit in MCH (which makes sense layout-wise). */
+ /* Note sure if this has any effect at all though. */
+ MCHBAR32(0x0004) |= 0x00001000;
+ MCHBAR32(0x0104) |= 0x00001000;
+}
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+static const u16 hwm_initvals[] = {
+ HWM_BANK(0),
+ HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */
+
+ HWM_BANK(7), /* PECI */
+ HWM_INITVAL(0x01, 0x95), /* Enable PECI */
+ HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */
+ /*
+ * PECI temperatures are negative, going up to 0.
+ * 0 represents the maximum allowable junction temperature, Tjmax.
+ * There is also Tcontrol, which is the temperature at which the
+ * system cooling should run at full speed.
+ * Since the NCT5577D fan control only supports positive values,
+ * Tbase0 is used as an offset.
+ */
+ HWM_INITVAL(0x09, CRITICAL_TEMPERATURE), /* Tbase0 */
+
+ HWM_BANK(2), /* CPUFAN control */
+ HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */
+ HWM_INITVAL(0x01, 50), /* Target temperature */
+ HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */
+ HWM_INITVAL(0x03, 0x01), /* Step-up time */
+ HWM_INITVAL(0x04, 0x01), /* Step-down time */
+ HWM_INITVAL(0x05, 0x10), /* Stop PWM value */
+ HWM_INITVAL(0x06, 0x20), /* Start PWM value */
+ HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */
+ HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */
+ HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */
+ HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */
+ HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */
+ HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */
+ HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */
+ HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */
+ /* Smart Fan IV Critical temp */
+ HWM_INITVAL(0x35, CRITICAL_TEMPERATURE),
+ HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */
+ HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */
+ HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */
+ HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */
+ HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */
+ HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */
+ HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */
+
+ HWM_BANK(0),
+};
+
+static void hwm_init(void)
+{
+ /* Set up fan control */
+ for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++)
+ HWM_WRITE_INITVAL(hwm_initvals[i]);
+}
+
+static const u16 superio_initvals[] = {
+ /* Global config registers */
+ SUPERIO_INITVAL(0x1a, 0x02),
+ SUPERIO_INITVAL(0x1b, 0x6a),
+ SUPERIO_INITVAL(0x27, 0x80),
+#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+ SUPERIO_INITVAL(0x2a, 0x80),
+#else
+ SUPERIO_INITVAL(0x2a, 0x00),
+#endif
+ SUPERIO_INITVAL(0x2c, 0x00),
+
+ SUPERIO_BANK(2), /* UART A */
+ SUPERIO_INITVAL(0x30, 0x01),
+ SUPERIO_INITVAL(0x60, 0x03),
+ SUPERIO_INITVAL(0x61, 0xf8),
+ SUPERIO_INITVAL(0x70, 0x04),
+
+ SUPERIO_BANK(7), /* GPIO config */
+ SUPERIO_INITVAL(0x30, 0x01),
+ SUPERIO_INITVAL(0xe0, 0xcf),
+ SUPERIO_INITVAL(0xe1, 0x0f),
+ SUPERIO_INITVAL(0xe4, 0xed),
+ SUPERIO_INITVAL(0xe5, 0x4d),
+ SUPERIO_INITVAL(0xec, 0x30),
+ SUPERIO_INITVAL(0xee, 0xff),
+
+ SUPERIO_BANK(8),
+ SUPERIO_INITVAL(0x30, 0x0a),
+ SUPERIO_INITVAL(0x60, GPIO_PORT >> 8),
+ SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff),
+
+ SUPERIO_BANK(9),
+ SUPERIO_INITVAL(0x30, 0x8c),
+ SUPERIO_INITVAL(0xe1, 0x90),
+
+ SUPERIO_BANK(0xa),
+ SUPERIO_INITVAL(0xe4, 0x20),
+ SUPERIO_INITVAL(0xe6, 0x4c),
+
+ SUPERIO_BANK(0xb), /* HWM & LED */
+ SUPERIO_INITVAL(0x30, 0x01),
+ SUPERIO_INITVAL(0x60, HWM_PORT >> 8),
+ SUPERIO_INITVAL(0x61, HWM_PORT & 0xff),
+ SUPERIO_INITVAL(0xf7, 0x67),
+ SUPERIO_INITVAL(0xf8, 0x60),
+
+ SUPERIO_BANK(0x16),
+ SUPERIO_INITVAL(0x30, 0x00),
+};
+
+static void superio_init(void)
+{
+ SUPERIO_UNLOCK;
+ for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++)
+ SUPERIO_WRITE_INITVAL(superio_initvals[i]);
+ SUPERIO_LOCK;
+}
+
+void mainboard_config_superio(void)
+{
+ superio_init();
+ hwm_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
+#include "usb.h"
+};
diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/dcp847ske/gma-mainboard.ads
new file mode 100644
index 0000000..493051e
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/gma-mainboard.ads
@@ -0,0 +1,28 @@
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; version 2 of
+-- the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ HDMI3,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/dcp847ske/gpio.c
new file mode 100644
index 0000000..5b07d80
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/gpio.c
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_NATIVE,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT, /* BIOS jumper: 1 = normal, 0 = setup */
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+/*
+ * GPIO8: RAM voltage: LOW: 1.5V, HIGH: 1.35V
+ * GPIO27: Set to HIGH on S3/S4/S5 by original fw dsdt.
+ * GPIO29: Actually NATIVE? Can't clear, stays 1.
+ * SLP_LAN# is affected by soft-strap according to docs.
+ * Others: No visible effect when toggling.
+ */
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_NATIVE,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT, /* mSATA presence detect */
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio68 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c
new file mode 100644
index 0000000..b000347
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c
new file mode 100644
index 0000000..5dc4ab6
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/mainboard.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/common/gpio.h>
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_DEBUG, "Memory voltage: %s\n",
+ get_gpio(8) ? "1.35V" : "1.5V");
+ printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n",
+ get_gpio(22) ? "normal (1-2)" : "setup (2-3)");
+ printk(BIOS_DEBUG, "mSATA: %s\n",
+ get_gpio(35) ? "present" : "absent");
+
+ install_intel_vga_int15_handler(
+ GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
new file mode 100644
index 0000000..ad31bba
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#else
+#include <northbridge/intel/sandybridge/raminit.h>
+#endif
+
+#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0,
+ .gbe_enable = 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1333,
+ .usb_port_config = {
+#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
+#include "usb.h"
+ },
+ };
+ *pei_data = pei_data_template;
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+#endif
diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/dcp847ske/smihandler.c
new file mode 100644
index 0000000..7ae3f39
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/smihandler.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <cpu/x86/smm.h>
+#include "superio.h"
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (slp_typ > 0 && slp_typ < 4) {
+ /* Enable GRN_LED [Power LED] fading */
+ SUPERIO_UNLOCK;
+ SUPERIO_WRITE(0xf7, 0x68);
+ SUPERIO_LOCK;
+ }
+}
diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h
new file mode 100644
index 0000000..56938e7
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/superio.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DCP847SKE_SUPERIO_H
+#define DCP847SKE_SUPERIO_H
+
+#include <arch/io.h>
+
+#define NUVOTON_PORT 0x4e
+#define HWM_PORT 0x0a30
+#define GPIO_PORT 0x0a80
+
+#define SUPERIO_BANK(x) (0x0700 | x)
+#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data))
+#define HWM_BANK(x) (0x4e00 | x)
+#define HWM_INITVAL SUPERIO_INITVAL
+
+#define SUPERIO_UNLOCK do { \
+ outb(0x87, NUVOTON_PORT); \
+ outb(0x87, NUVOTON_PORT); \
+} while (0)
+
+#define SUPERIO_LOCK do { \
+ outb(0xaa, NUVOTON_PORT); \
+} while (0)
+
+#define SUPERIO_WRITE(reg, data) do { \
+ outb((reg), NUVOTON_PORT); \
+ outb((data), NUVOTON_PORT + 1); \
+} while (0)
+
+#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff)
+
+#define HWM_WRITE(reg, data) do { \
+ outb((reg), HWM_PORT + 5); \
+ outb((data), HWM_PORT + 6); \
+} while (0)
+
+#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff)
+
+#endif /* DCP847SKE_SUPERIO_H */
diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h
new file mode 100644
index 0000000..914b323
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DCP847SKE_THERMAL_H
+#define DPC847SKE_THERMAL_H
+
+/* TODO: These should be generated at runtime from
+ * MSR_TEMPERATURE_TARGET (0x1a2) */
+
+/* Temperature which OS will shutdown at (Tjmax) */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU (Tcontrol) */
+#define PASSIVE_TEMPERATURE 86
+
+#endif
diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h
new file mode 100644
index 0000000..c6a5295
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/usb.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DCP847SKE_USB_H
+#define DPC847SKE_USB_H
+
+USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */
+USB_CONFIG(1, 1, 0), /* back, towards power plug */
+USB_CONFIG(1, 1, 1), /* half-width miniPCIe */
+USB_CONFIG(1, 1, 1), /* full-width miniPCIe */
+USB_CONFIG(1, 1, 2), /* front-panel header */
+USB_CONFIG(1, 1, 2), /* front-panel header */
+USB_CONFIG(1, 1, 3), /* front connector */
+USB_CONFIG(0, 1, 3), /* not available */
+USB_CONFIG(0, 1, 4), /* not available */
+USB_CONFIG(0, 1, 4), /* not available */
+USB_CONFIG(0, 1, 5), /* not available */
+USB_CONFIG(0, 1, 5), /* not available */
+USB_CONFIG(0, 1, 6), /* not available */
+USB_CONFIG(0, 1, 6), /* not available */
+
+#endif