tree 8d58912b24225531e777559579dfaecee37e647b
parent e9984c8e4fec24c2fe6320b2b6726f13ed7d7296
author Aamir Bohra <aamir.bohra@intel.com> 1599642276 +0530
committer Patrick Georgi <pgeorgi@google.com> 1602492732 +0000

mb/google/dedede: Enable SaGv support

Allow MRC training in SaGv low, mid and high frequencies.

TEST=Verify memory trains at low, mid and high SaGv point
     through FSP debug logs enabled.

Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>