diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index b1ac3d1..0d90175 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -3,14 +3,16 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <device/pci_ops.h>
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <device/pci_ops.h>
 #include <program_loading.h>
+#include <stdint.h>
+
 #include "e7505.h"
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	uintptr_t tolm;
@@ -19,7 +21,7 @@
 	tolm = pci_read_config16(mch, TOLM) >> 11;
 	tolm <<= 27;
 
-	return (void *)tolm;
+	return tolm;
 }
 
 void northbridge_write_smram(u8 smram);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 28edb38..35ec41d 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -104,10 +104,9 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
-	return (void *) top_of_ram;
+	return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 }
 
 void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index c19cfec..6b75caa 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -54,9 +54,9 @@
 	return tolum;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)top_of_low_usable_memory();
+	return top_of_low_usable_memory();
 }
 
 void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index b6d9526..5cee1b4 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -8,7 +8,7 @@
 #include <program_loading.h>
 #include "i440bx.h"
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	/* Base of TSEG is top of usable DRAM */
 	/*
@@ -39,7 +39,7 @@
 	 *
 	 * Source: 440BX datasheet, pages 3-28 thru 3-29.
 	 */
-	unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB;
+	uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB;
 
 	int gsmrame = pci_read_config8(NB, SMRAM) & 0x8;
 	/* T_SZ and TSEG_EN */
@@ -48,7 +48,7 @@
 		int tseg_size = 128 * KiB * (1 << (tseg >> 1));
 		tom -= tseg_size;
 	}
-	return (void *)tom;
+	return tom;
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 1fa0358..e0352fb 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -57,10 +57,9 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
-	return (void *) top_of_ram;
+	return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 }
 
 /* Decodes used Graphics Mode Select (GMS) to kilobytes. */
diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index 78fbae8..bdb76c1 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -22,9 +22,9 @@
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)northbridge_get_tseg_base();
+	return northbridge_get_tseg_base();
 }
 
 void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index c02cf35..55d7046 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -73,9 +73,9 @@
  * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
  * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
+	return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
 
 }
 
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index f667544..ac95ab5 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -54,9 +54,9 @@
 	return tolum;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)top_of_low_usable_memory();
+	return top_of_low_usable_memory();
 }
 
 void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index dced902..0b085cf 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -71,10 +71,9 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
-	return (void *) top_of_ram;
+	return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 }
 
 void smm_region(uintptr_t *start, size_t *size)