soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3983d03..a6932bc 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -110,6 +110,9 @@
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 19b9300..f525fd8 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -104,6 +104,10 @@
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+ /* Enable ClkReqDetect for enabled port */
+ memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+ sizeof(config->PcieRpClkReqDetect));
+
/* USB configuration */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {