tree d131317e6aa618199afb44c58063fca393914527
parent 7e7cc1a8c9a87e33bd772e8526734c7a82ec2db7
author Usha P <usha.p@intel.com> 1638251858 +0530
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1638566977 +0000

soc/intel/alderlake: Add support for ADL-N PCH

Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.

Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.

Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>