tree 8f379905bc56f3ca2479dcbc324b58c3cbef9cf7
parent 9f5b2f75ad5c500dbe8a3d9f27e6107fd56ee76d
author Felix Held <felix-coreboot@felixheld.de> 1678154907 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1678306509 +0000

soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h

The bit position of the P state enable bit in the 8 P state MSRs is
identical for all AMD chips including the family 16h model 30h APU that
lives outside of soc/amd. The other bits in those 8 MSRs are more or
less family- and model-specific.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>