tree 444c80a1388edca1e80e7ee0c72ba893ac0479d2
parent 7ee7b137a7638f5e9d85bd88e52e6391da0ebcbb
author Tyler Wang <tyler.wang@quanta.corp-partner.google.com> 1709865597 +0800
committer Felix Held <felix-coreboot@felixheld.de> 1710338422 +0000

soc/intel/mtl: Improve functions in soc_info.c

Remove debug message since it's static information.
Remove additional uint_8 varience and return below settings
directly:
1. CONFIG_SOC_INTEL_USB2_DEV_MAX
2. CONFIG_SOC_INTEL_USB3_DEV_MAX
3. MAX_TYPE_C_PORTS
4. CONFIG_MAX_TBT_ROOT_PORTS
5. CONFIG_MAX_ROOT_PORTS
6. CONFIG_MAX_PCIE_CLOCK_SRC
7. CONFIG_SOC_INTEL_UART_DEV_MAX
8. CONFIG_SOC_INTEL_I2C_DEV_MAX
9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX

BUG=none
TEST=Build and test on rex/karis, system can boot to OS

Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>