commit | 7848aa9335e764952d50f05f9c66cfbf70291ec0 | [log] [tgz] |
---|---|---|
author | Subrata Banik <subratabanik@google.com> | Tue Feb 15 20:49:01 2022 +0530 |
committer | Felix Held <felix-coreboot@felixheld.de> | Fri Feb 18 20:23:33 2022 +0000 |
tree | 6fadac698f452b428cb5222c23579f480e82d4c0 | |
parent | 95986169f93efe8b99c5b7d4a0fff3b5541d1377 [diff] |
soc/intel/denverton_ns: Add function to clear PMCON status bits This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579. Additionally, removed `PMC_` prefix from PMC configuration register macros GEN_PMCON_A/B and ETR3. Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on function numbers. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.