soc/mediatek/mt8186: Add DDP driver
Add DDP (display controller) driver that supports main path to
eDP panel. The output goes to display interface DSI.
BUG=b:209930699
TEST=saw firmware display
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc
index c940d37..dd7541f 100644
--- a/src/soc/mediatek/mt8186/Makefile.inc
+++ b/src/soc/mediatek/mt8186/Makefile.inc
@@ -44,6 +44,7 @@
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += ../common/auxadc.c
+ramstage-y += ../common/ddp.c ddp.c
ramstage-y += devapc.c
ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c
new file mode 100644
index 0000000..6706ed7
--- /dev/null
+++ b/src/soc/mediatek/mt8186/ddp.c
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 6.9
+ */
+
+#include <console/console.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+static void disp_config_main_path_connection(void)
+{
+ /*
+ * Main path:
+ * OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->DITHER->DSI0
+ */
+ SET32_BITFIELDS(&mmsys_cfg->disp_ovl0_mout_en,
+ DISP_OVL0_MOUT_EN, DISP_OVL0_MOUT_TO_RDMA0);
+ SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sel_in,
+ DISP_RDMA0_SEL_IN, DISP_RDMA0_FROM_OVL0);
+ SET32_BITFIELDS(&mmsys_cfg->mmsys_ovl_con,
+ DISP_MMSYS_OVL0_CON, DISP_OVL0_GO_BLEND);
+ SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sout_sel,
+ DISP_RDMA0_SOUT_SEL, DISP_RDMA0_SOUT_TO_COLOR0);
+ SET32_BITFIELDS(&mmsys_cfg->disp_dither0_mout_en,
+ DISP_DITHER0_MOUT_EN, DISP_DITHER0_MOUT_TO_DSI0);
+ SET32_BITFIELDS(&mmsys_cfg->disp_dsi0_sel_in,
+ DISP_DSI0_SEL_IN, DISP_DSI0_FROM_DITHER0);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+ write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+ /* Clock source from DSI0 */
+ write32(&disp_mutex->mutex[0].ctl,
+ MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+ write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_layer_smi_id_en(u32 idx)
+{
+ SET32_BITFIELDS(&disp_ovl[idx]->datapath_con,
+ SMI_ID_EN, SMI_ID_EN_VAL);
+}
+
+static void ccorr_config(u32 width, u32 height)
+{
+ struct disp_ccorr_regs *const regs = disp_ccorr;
+
+ write32(®s->size, width << 16 | height);
+
+ /* Disable relay mode */
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, 0);
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_ENGINE_EN, PQ_ENGINE_EN);
+
+ write32(®s->en, PQ_EN);
+}
+
+static void aal_config(u32 width, u32 height)
+{
+ struct disp_aal_regs *const regs = disp_aal;
+
+ write32(®s->size, width << 16 | height);
+ write32(®s->output_size, width << 16 | height);
+
+ /* Enable relay mode */
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE);
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_ENGINE_EN, 0);
+
+ write32(®s->en, PQ_EN);
+}
+
+static void gamma_config(u32 width, u32 height)
+{
+ struct disp_gamma_regs *const regs = disp_gamma;
+
+ write32(®s->size, width << 16 | height);
+
+ /* Disable relay mode */
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, 0);
+
+ write32(®s->en, PQ_EN);
+}
+
+static void postmask_config(u32 width, u32 height)
+{
+ struct disp_postmask_regs *const regs = disp_postmask;
+
+ write32(®s->size, width << 16 | height);
+
+ /* Enable relay mode */
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE);
+
+ write32(®s->en, PQ_EN);
+}
+
+static void dither_config(u32 width, u32 height)
+{
+ struct disp_dither_regs *const regs = disp_dither;
+
+ write32(®s->size, width << 16 | height);
+
+ /* Enable relay mode */
+ SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE);
+
+ write32(®s->en, PQ_EN);
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+ u32 pixel_clk = width * height * vrefresh;
+
+ /* One ovl in main path */
+ ovl_set_roi(0, width, height, 0xff0000ff);
+ ovl_layer_smi_id_en(0);
+ rdma_config(width, height, pixel_clk, 5 * KiB);
+ color_start(width, height);
+ ccorr_config(width, height);
+ aal_config(width, height);
+ gamma_config(width, height);
+ postmask_config(width, height);
+ dither_config(width, height);
+ disp_config_main_path_connection();
+ disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+ clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+ clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL);
+}
+
+void mtk_ddp_init(void)
+{
+ disp_clock_on();
+
+ /* Turn off M4U port */
+ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+ u32 fmt = OVL_INFMT_RGBA8888;
+ u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+ u32 width = edid->mode.ha;
+ u32 height = edid->mode.va;
+ u32 vrefresh = edid->mode.refresh;
+
+ printk(BIOS_INFO, "%s: display resolution: %ux%u@%u bpp %u\n",
+ __func__, width, height, vrefresh, bpp);
+
+ if (!vrefresh) {
+ vrefresh = 60;
+ printk(BIOS_INFO, "%s: invalid vrefresh; setting to %u\n",
+ __func__, vrefresh);
+ }
+
+ main_disp_path_setup(width, height, vrefresh);
+ rdma_start();
+ ovl_layer_config(fmt, bpp, width, height);
+}
diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h
index adb1d59..c90e0cd 100644
--- a/src/soc/mediatek/mt8186/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h
@@ -75,8 +75,19 @@
EFUSEC_BASE = IO_PHYS + 0x01CB0000,
MIPITX_BASE = IO_PHYS + 0x01CC0000,
MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000,
+ MMSYS_BASE = IO_PHYS + 0x04000000,
+ DISP_MUTEX_BASE = IO_PHYS + 0x04001000,
SMI_BASE = IO_PHYS + 0x04002000,
SMI_LARB0 = IO_PHYS + 0x04003000,
+ DISP_OVL0_BASE = IO_PHYS + 0x04005000,
+ DISP_OVL1_BASE = IO_PHYS + 0x04006000,
+ DISP_RDMA0_BASE = IO_PHYS + 0x04007000,
+ DISP_COLOR0_BASE = IO_PHYS + 0x04009000,
+ DISP_CCORR0_BASE = IO_PHYS + 0x0400B000,
+ DISP_AAL0_BASE = IO_PHYS + 0x0400C000,
+ DISP_GAMMA0_BASE = IO_PHYS + 0x0400D000,
+ DISP_POSTMASK0_BASE = IO_PHYS + 0x0400E000,
+ DISP_DITHER0_BASE = IO_PHYS + 0x0400F000,
DSI0_BASE = IO_PHYS + 0x04013000,
};
#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h
new file mode 100644
index 0000000..e66563d
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/ddp.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 6.9
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_DDP_H
+#define SOC_MEDIATEK_MT8186_DDP_H
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/ddp_common.h>
+#include <types.h>
+
+#define SMI_LARB_PORT_L0_OVL_RDMA0 0x388
+
+struct mmsys_cfg_regs {
+ u32 reserved_0x000[64]; /* 0x000 */
+ u32 mmsys_cg_con0; /* 0x100 */
+ u32 mmsys_cg_set0; /* 0x104 */
+ u32 mmsys_cg_clr0; /* 0x108 */
+ u32 reserved_0x10c; /* 0x10C */
+ u32 mmsys_cg_con1; /* 0x110 */
+ u32 mmsys_cg_set1; /* 0x114 */
+ u32 mmsys_cg_clr1; /* 0x118 */
+ u32 reserved_0x11c[33]; /* 0x11C */
+ u32 mmsys_cg_con2; /* 0x1A0 */
+ u32 mmsys_cg_set2; /* 0x1A4 */
+ u32 mmsys_cg_clr2; /* 0x1A8 */
+ u32 reserved_0x1ac[853]; /* 0x1AC */
+ u32 reserved_0xf00; /* 0xF00 */
+ u32 mmsys_ovl_con; /* 0xF04 */
+ u32 reserved_0xf08; /* 0xF08 */
+ u32 disp_rdma0_sout_sel; /* 0xF0C */
+ u32 reserved_0xf10; /* 0xF10 */
+ u32 disp_ovl0_2l_mout_en; /* 0xF14 */
+ u32 disp_ovl0_mout_en; /* 0xF18 */
+ u32 reserved_0xf1c; /* 0xF1C */
+ u32 disp_dither0_mout_en; /* 0xF20 */
+ u32 reserved_0xf24; /* 0xF24 */
+ u32 disp_rdma0_sel_in; /* 0xF28 */
+ u32 reserved_0xf2c; /* 0xF2C */
+ u32 disp_dsi0_sel_in; /* 0xF30 */
+ u32 reserved_0xf34[2]; /* 0xF34 */
+ u32 disp_rdma1_mout_en; /* 0xF3C */
+ u32 disp_rdma1_sel_in; /* 0xF40 */
+ u32 disp_dpi0_sel_in; /* 0xF44 */
+};
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110);
+check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0);
+check_member(mmsys_cfg_regs, mmsys_ovl_con, 0xF04);
+check_member(mmsys_cfg_regs, disp_rdma0_sout_sel, 0xF0C);
+check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF18);
+check_member(mmsys_cfg_regs, disp_dither0_mout_en, 0xF20);
+check_member(mmsys_cfg_regs, disp_rdma0_sel_in, 0xF28);
+check_member(mmsys_cfg_regs, disp_dsi0_sel_in, 0xF30);
+
+struct disp_mutex_regs {
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[6];
+ struct {
+ u32 en;
+ u32 dummy;
+ u32 rst;
+ u32 ctl;
+ u32 mod;
+ u32 reserved[3];
+ } mutex[16];
+};
+
+struct disp_ccorr_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[27];
+ u32 shadow;
+};
+check_member(disp_ccorr_regs, shadow, 0xA0);
+
+struct disp_gamma_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+check_member(disp_gamma_regs, size, 0x30);
+
+struct disp_aal_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[47];
+ u32 shadow;
+ u32 reserved3[249];
+ u32 output_size;
+};
+check_member(disp_aal_regs, shadow, 0xF0);
+check_member(disp_aal_regs, output_size, 0x4D8);
+
+struct disp_postmask_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[4];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+check_member(disp_postmask_regs, size, 0x30);
+
+struct disp_dither_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[51];
+ u32 disp_dither_0;
+};
+check_member(disp_dither_regs, disp_dither_0, 0x100);
+
+/*
+ * DISP_REG_CONFIG_MMSYS_CG_CON0
+ * Configures free-run clock gating 0
+ * 0: Enable clock
+ * 1: Clock gating
+ */
+enum {
+ CG_CON0_DISP_MUTEX0 = BIT(0),
+ CG_CON0_APB_MM_BUS = BIT(1),
+ CG_CON0_DISP_OVL0 = BIT(2),
+ CG_CON0_DISP_RDMA0 = BIT(3),
+ CG_CON0_DISP_OVL0_2L = BIT(4),
+ CG_CON0_DISP_WDMA0 = BIT(5),
+ CG_CON0_DISP_RSZ0 = BIT(7),
+ CG_CON0_DISP_AAL0 = BIT(8),
+ CG_CON0_DISP_CCORR0 = BIT(9),
+ CG_CON0_DISP_COLOR0 = BIT(10),
+ CG_CON0_SMI_INFRA = BIT(11),
+ CG_CON0_DISP_GAMMA0 = BIT(13),
+ CG_CON0_DISP_POSTMASK0 = BIT(14),
+ CG_CON0_DISP_DITHER0 = BIT(16),
+ CG_CON0_SMI_COMMON = BIT(17),
+ CG_CON0_DISP_DSI0 = BIT(19),
+ CG_CON0_DISP_FAKE_ENG0 = BIT(20),
+ CG_CON0_DISP_FAKE_ENG1 = BIT(21),
+ CG_CON0_SMI_GALS = BIT(22),
+ CG_CON0_SMI_IOMMU = BIT(24),
+ CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 |
+ CG_CON0_APB_MM_BUS |
+ CG_CON0_DISP_OVL0 |
+ CG_CON0_DISP_RDMA0 |
+ CG_CON0_DISP_AAL0 |
+ CG_CON0_DISP_CCORR0 |
+ CG_CON0_DISP_COLOR0 |
+ CG_CON0_SMI_INFRA |
+ CG_CON0_DISP_GAMMA0 |
+ CG_CON0_DISP_POSTMASK0 |
+ CG_CON0_DISP_DITHER0 |
+ CG_CON0_SMI_COMMON |
+ CG_CON0_DISP_DSI0 |
+ CG_CON0_SMI_GALS |
+ CG_CON0_SMI_IOMMU,
+ CG_CON0_ALL = 0xFFFFFFFF,
+};
+
+enum {
+ CG_CON2_DSI0_DSI_CK_DOMAIN = BIT(0),
+ CG_CON2_DISP_26M = BIT(10),
+ CG_CON2_DISP_ALL = CG_CON2_DSI0_DSI_CK_DOMAIN |
+ CG_CON2_DISP_26M,
+ CG_CON2_ALL = 0xFFFFFFFF,
+};
+
+DEFINE_BITFIELD(DISP_OVL0_MOUT_EN, 3, 0)
+DEFINE_BITFIELD(DISP_RDMA0_SEL_IN, 3, 0)
+DEFINE_BITFIELD(DISP_MMSYS_OVL0_CON, 1, 0)
+DEFINE_BITFIELD(DISP_RDMA0_SOUT_SEL, 3, 0)
+DEFINE_BITFIELD(DISP_DITHER0_MOUT_EN, 3, 0)
+DEFINE_BITFIELD(DISP_DSI0_SEL_IN, 3, 0)
+
+DEFINE_BIT(SMI_ID_EN, 0)
+DEFINE_BIT(PQ_CFG_RELAY_MODE, 0)
+DEFINE_BIT(PQ_CFG_ENGINE_EN, 1)
+
+#define DISP_OVL0_MOUT_TO_RDMA0 BIT(0)
+#define DISP_RDMA0_FROM_OVL0 0
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_RDMA0_SOUT_TO_COLOR0 1
+#define DISP_DITHER0_MOUT_TO_DSI0 BIT(0)
+#define DISP_DSI0_FROM_DITHER0 1
+
+#define SMI_ID_EN_VAL BIT(0)
+
+enum {
+ MUTEX_MOD_DISP_OVL0 = BIT(0),
+ MUTEX_MOD_DISP_RDMA0 = BIT(2),
+ MUTEX_MOD_DISP_COLOR0 = BIT(4),
+ MUTEX_MOD_DISP_CCORR0 = BIT(5),
+ MUTEX_MOD_DISP_AAL0 = BIT(7),
+ MUTEX_MOD_DISP_GAMMA0 = BIT(8),
+ MUTEX_MOD_DISP_POSTMASK0 = BIT(9),
+ MUTEX_MOD_DISP_DITHER0 = BIT(10),
+ MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 |
+ MUTEX_MOD_DISP_RDMA0 |
+ MUTEX_MOD_DISP_COLOR0 |
+ MUTEX_MOD_DISP_CCORR0 |
+ MUTEX_MOD_DISP_AAL0 |
+ MUTEX_MOD_DISP_GAMMA0 |
+ MUTEX_MOD_DISP_POSTMASK0 |
+ MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+ MUTEX_SOF_SINGLE_MODE = 0,
+ MUTEX_SOF_DSI0 = 1,
+ MUTEX_SOF_DPI0 = 2,
+};
+
+#define PQ_EN BIT(0)
+#define PQ_RELAY_MODE BIT(0)
+#define PQ_ENGINE_EN BIT(1)
+
+static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE;
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE;
+static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif