diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index dc70a4f..eb67012 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -18,9 +18,10 @@
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
-#include <intelblocks/rtc.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
 #include <intelblocks/smbus.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
@@ -50,25 +51,6 @@
 #define PCR_DMI_LPCIOD		0x2770
 #define PCR_DMI_LPCIOE		0x2774
 
-static void enable_p2sbbar(void)
-{
-	pci_devfn_t dev = PCH_DEV_P2SB;
-
-	/* Enable PCR Base address in PCH */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
-
-	/* Enable P2SB MSE */
-	pci_write_config8(dev, PCI_COMMAND,
-			  PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-	/*
-	 * Enable decoding for HPET memory address range.
-	 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
-	 * the High Performance Timer memory address range
-	 * selected by bits 1:0
-	 */
-	pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
-}
-
 static void soc_config_pwrmbase(void)
 {
 	uint32_t reg32;
@@ -96,7 +78,8 @@
 {
 	fast_spi_early_init(SPI_BASE_ADDRESS);
 	gspi_early_bar_init();
-	enable_p2sbbar();
+	p2sb_enable_bar();
+	p2sb_configure_hpet();
 	/*
 	 * Enabling PWRM Base for accessing
 	 * Global Reset Cause Register.