Falco/Slippy: Patch to refactor haswell/gma.c and mainboard/google/slippy/i915io.c
A large portion of documented registers have been initialized using macros. Only a few
undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant
calls. However, some more work is required to correctly identify which calls are not required.
All the io_writes are replaced by gtt_writes.
Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66204
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6600
Tested-by: build bot (Jenkins)
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 9ef3abd..72301e1 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -63,6 +63,12 @@
TRANSCODER_EDP = 0xF,
};
+enum plane {
+ PLANE_A = 0,
+ PLANE_B,
+ PLANE_C,
+};
+
/* debug enums. These are for printks that, due to their place in the
* middle of graphics device IO, might change timing. Use with care
* or not at all.
@@ -132,6 +138,7 @@
u32 clock;
int port;
int pipe;
+ int plane;
int bpp;
/* i2c on aux is ... interesting.
* Before you do an i2c cycle, you need to set the address.
@@ -193,7 +200,6 @@
void ironlake_edp_panel_on(struct intel_dp *intel_dp);
void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
/* needed only on haswell. */
-void intel_prepare_ddi_buffers(int port, int use_fdi_mode);
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port);
int intel_dp_aux_ch(struct intel_dp *intel_dp,
uint8_t *send, int send_bytes,
@@ -262,3 +268,12 @@
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
u8 *recv);
+
+void intel_prepare_ddi(void);
+void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
+
+void gtt_write(u32 reg, u32 data);
+u32 gtt_read(u32 reg);
+
+int i915lightup(unsigned int physbase, unsigned int mmio,
+ unsigned int gfx, unsigned int init_fb);
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index cbb0628..2ee5748 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -1672,6 +1672,7 @@
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
#define BLC_PWM_CPU_CTL2 0x48250
+#define BLC_PWM2_ENABLE (1<<31)
#define BLC_PWM_CPU_CTL 0x48254
#define BLM_HIST_CTL 0x48260
@@ -2978,6 +2979,7 @@
/* Ironlake */
#define CPU_VGACNTRL 0x41000
+#define CPU_VGA_DISABLE (1<<31)
#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
@@ -4391,4 +4393,8 @@
#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
#define WM_DBG_DISALLOW_SPRITE (1<<2)
+/* North Display Engine Reset Warn Options */
+#define NDE_RSTWRN_OPT 0x46408
+#define RST_PCH_HNDSHK_EN (1<<4)
+
#endif /* _I915_REG_H_ */
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 3b7dc6d..2b27f6e 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -87,7 +87,7 @@
* in either FDI or DP modes only, as HDMI connections will work with both
* of those.
*/
-void intel_prepare_ddi_buffers(int port, int use_fdi_mode)
+static void intel_prepare_ddi_buffers(int port, int use_fdi_mode)
{
u32 reg;
int i;
@@ -100,11 +100,22 @@
use_fdi_mode ? "FDI" : "DP");
for (i=0,reg=DDI_BUF_TRANS(port);i < ARRAY_SIZE(hsw_ddi_translations_fdi);i++) {
- io_i915_write32(ddi_translations[i], reg);
+ gtt_write(reg,ddi_translations[i]);
reg += 4;
}
}
+void intel_prepare_ddi(void)
+{
+ int port;
+ u32 use_fdi = 1;
+
+ for (port = PORT_A; port < PORT_E; port++)
+ intel_prepare_ddi_buffers(port, !use_fdi);
+
+ intel_prepare_ddi_buffers(PORT_E, use_fdi);
+}
+
static void intel_wait_ddi_buf_idle(int port)
{
uint32_t reg = DDI_BUF_CTL(port);
@@ -112,7 +123,7 @@
for (i = 0; i < 8; i++) {
udelay(1);
- if (io_i915_read32(reg) & DDI_BUF_IS_IDLE){
+ if (gtt_read(reg) & DDI_BUF_IS_IDLE){
printk(BIOS_SPEW, "%s: buf is idle (success)\n", __func__);
return;
}
@@ -126,18 +137,18 @@
int wait = 0;
uint32_t val;
- if (io_i915_read32(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
- val = io_i915_read32(DDI_BUF_CTL(port));
+ if (gtt_read(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ val = gtt_read(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
- io_i915_write32(DDI_BUF_CTL(port), val);
+ gtt_write(val,DDI_BUF_CTL(port));
wait = 1;
}
- val = io_i915_read32(DP_TP_CTL(port));
+ val = gtt_read(DP_TP_CTL(port));
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- io_i915_write32(DP_TP_CTL(port), val);
+ gtt_write(val,DP_TP_CTL(port));
//POSTING_READ(DP_TP_CTL(port));
if (wait)
@@ -148,11 +159,11 @@
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
- io_i915_write32(DP_TP_CTL(port), val);
+ gtt_write(val,DP_TP_CTL(port));
//POSTING_READ(DP_TP_CTL(port));
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- io_i915_write32(DDI_BUF_CTL(port), intel_dp->DP);
+ gtt_write(intel_dp->DP,DDI_BUF_CTL(port));
//POSTING_READ(DDI_BUF_CTL(port));
udelay(600);
@@ -237,3 +248,26 @@
return TRANSCODER_EDP;
return (enum transcoder)pipe;
}
+
+void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
+{
+ u32 val = TRANS_MSA_SYNC_CLK;
+
+ switch (intel_dp->bpp) {
+ case 18:
+ val |= TRANS_MSA_6_BPC;
+ break;
+ case 24:
+ val |= TRANS_MSA_8_BPC;
+ break;
+ case 30:
+ val |= TRANS_MSA_10_BPC;
+ break;
+ case 36:
+ val |= TRANS_MSA_12_BPC;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->bpp);
+ }
+ gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
+}
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 44a947e..833a4d6 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -98,12 +98,12 @@
static int ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
- return (io_i915_read32(PCH_PP_STATUS) & PP_ON) != 0;
+ return (gtt_read(PCH_PP_STATUS) & PP_ON) != 0;
}
static int ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
- return (io_i915_read32(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+ return (gtt_read(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
}
int
@@ -121,7 +121,7 @@
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
- status = io_i915_read32(ch_ctl);
+ status = gtt_read(ch_ctl);
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
break;
mdelay(1);
@@ -129,7 +129,7 @@
if (try == 3) {
if (1) {
- status = io_i915_read32(ch_ctl);
+ status = gtt_read(ch_ctl);
printk(BIOS_ERR,
"dp_aux_ch not started status 0x%08x\n",
status);
@@ -144,30 +144,30 @@
u32 val, addr;
val = pack_aux(send + i, send_bytes - i);
addr = ch_data + i;
- io_i915_write32(val, addr);
+ gtt_write(addr,val);
}
/* Send the command and wait for it to complete */
- io_i915_write32(DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_TIME_OUT_400us |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (intel_dp->precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
- (intel_dp->aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
+ gtt_write(ch_ctl, DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_TIME_OUT_400us |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ (intel_dp->precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (intel_dp->aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
for (;;) {
- status = io_i915_read32(ch_ctl);
+ status = gtt_read(ch_ctl);
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
break;
udelay(100);
}
/* Clear done status and any errors */
- io_i915_write32(status |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
+ gtt_write(ch_ctl, status |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR))
@@ -204,7 +204,7 @@
recv_bytes = recv_size;
for (i = 0; i < recv_bytes; i += 4)
- unpack_aux(io_i915_read32(ch_data + i),
+ unpack_aux(gtt_read(ch_data + i),
recv + i, recv_bytes - i);
return recv_bytes;
@@ -513,13 +513,11 @@
intel_dp->clock, intel_dp->clock, &m_n);
{
- io_i915_write32((
- (m_n.tu - 1) <<
- PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
- m_n.gmch_m, TRANSDATA_M1(pipe));
- io_i915_write32(m_n.gmch_n, TRANSDATA_N1(pipe));
- io_i915_write32(m_n.link_m, TRANSDPLINK_M1(pipe));
- io_i915_write32(m_n.link_n, TRANSDPLINK_N1(pipe));
+ gtt_write(TRANSDATA_M1(pipe),
+ ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |m_n.gmch_m);
+ gtt_write(TRANSDATA_N1(pipe),m_n.gmch_n);
+ gtt_write(TRANSDPLINK_M1(pipe),m_n.link_m);
+ gtt_write(TRANSDPLINK_N1(pipe),m_n.link_n);
}
}
@@ -556,7 +554,7 @@
/* Preserve the BIOS-computed detected bit. This is
* supposed to be read-only.
*/
- intel_dp->DP = io_i915_read32(intel_dp->output_reg) & DP_DETECTED;
+ intel_dp->DP = gtt_read(intel_dp->output_reg) & DP_DETECTED;
printk(BIOS_SPEW, "%s: initial value is %08lx\n", __func__,
(unsigned long)intel_dp->DP);
/* | 0 essentially */
@@ -654,18 +652,18 @@
printk(BIOS_ERR, "[000000.0] [drm:%s], ", __func__);
printk(BIOS_ERR, "mask %08lx value %08lx status %08lx control %08lx\n",
(unsigned long) mask, (unsigned long) value,
- (unsigned long)io_i915_read32(PCH_PP_STATUS),
- (unsigned long)io_i915_read32(PCH_PP_CONTROL));
+ (unsigned long)gtt_read(PCH_PP_STATUS),
+ (unsigned long)gtt_read(PCH_PP_CONTROL));
- for(i = 0, status = io_i915_read32(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
- status = io_i915_read32(PCH_PP_STATUS)){
+ for(i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
+ status = gtt_read(PCH_PP_STATUS)){
udelay(10);
}
if (i > 5000){
printk(BIOS_ERR,
"Panel status timeout: status %08lx control %08lx\n",
- (unsigned long)io_i915_read32(PCH_PP_STATUS),
- (unsigned long)io_i915_read32(PCH_PP_CONTROL));
+ (unsigned long)gtt_read(PCH_PP_STATUS),
+ (unsigned long)gtt_read(PCH_PP_CONTROL));
}
}
@@ -693,7 +691,7 @@
unsigned long newval;
int tries = 0;
- while ((newval = io_i915_read32(addr)) != val) {
+ while ((newval = gtt_read(addr)) != val) {
udelay(1);
if (tries++ > 1000) {
printk(BIOS_ERR, "%s: Waiting on %08lx to be %08lx, got %08lx\n",
@@ -714,7 +712,7 @@
static u32 ironlake_get_pp_control(void)
{
- u32 control = io_i915_read32(PCH_PP_CONTROL);
+ u32 control = gtt_read(PCH_PP_CONTROL);
control &= ~PANEL_UNLOCK_MASK;
control |= PANEL_UNLOCK_REGS;
@@ -745,11 +743,12 @@
pp = ironlake_get_pp_control();
pp |= EDP_FORCE_VDD;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
// remember this if we need it later. Not sure yet.
////POSTING_READ(PCH_PP_CONTROL);
printk(BIOS_ERR, "PCH_PP_STATUS: 0x%08lx PCH_PP_CONTROL: 0x%08lx\n",
- io_i915_read32(PCH_PP_STATUS), io_i915_read32(PCH_PP_CONTROL));
+ (unsigned long) gtt_read(PCH_PP_STATUS),
+ (unsigned long) gtt_read(PCH_PP_CONTROL));
/*
* If the panel wasn't on, delay before accessing aux channel
@@ -767,12 +766,13 @@
if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
pp = ironlake_get_pp_control();
pp &= ~EDP_FORCE_VDD;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
/* Make sure sequencer is idle before allowing subsequent activity */
printk(BIOS_ERR, "PCH_PP_STATUS: 0x%08lx PCH_PP_CONTROL: 0x%08lx\n",
- io_i915_read32(PCH_PP_STATUS), io_i915_read32(PCH_PP_CONTROL));
+ (unsigned long) gtt_read(PCH_PP_STATUS),
+ (unsigned long) gtt_read(PCH_PP_CONTROL));
mdelay(intel_dp->panel_power_down_delay);
}
@@ -814,7 +814,7 @@
if (intel_dp->gen == 5) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
}
@@ -822,14 +822,14 @@
if (!(intel_dp->gen == 5))
pp |= PANEL_POWER_RESET;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
ironlake_wait_panel_on(intel_dp);
if (intel_dp->gen == 5) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
}
}
@@ -850,7 +850,7 @@
pp = ironlake_get_pp_control();
pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD |
PANEL_POWER_RESET | EDP_BLC_ENABLE);
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
ironlake_wait_panel_off(intel_dp);
@@ -872,7 +872,7 @@
mdelay(intel_dp->backlight_on_delay);
pp = ironlake_get_pp_control();
pp |= EDP_BLC_ENABLE;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
}
@@ -885,7 +885,7 @@
pp = ironlake_get_pp_control();
pp &= ~EDP_BLC_ENABLE;
- io_i915_write32(pp, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,pp);
////POSTING_READ(PCH_PP_CONTROL);
mdelay(intel_dp->backlight_off_delay);
}
@@ -894,9 +894,9 @@
{
u32 dpa_ctl;
- dpa_ctl = io_i915_read32(DP_A);
+ dpa_ctl = gtt_read(DP_A);
dpa_ctl |= DP_PLL_ENABLE;
- io_i915_write32(dpa_ctl, DP_A);
+ gtt_write(DP_A,dpa_ctl);
////POSTING_READ(DP_A);
udelay(200);
}
@@ -905,9 +905,9 @@
{
u32 dpa_ctl;
- dpa_ctl = io_i915_read32(DP_A);
+ dpa_ctl = gtt_read(DP_A);
dpa_ctl &= ~DP_PLL_ENABLE;
- io_i915_write32(dpa_ctl, DP_A);
+ gtt_write(DP_A,dpa_ctl);
////POSTING_READ(DP_A);
udelay(200);
}
@@ -981,7 +981,7 @@
void
intel_dp_dpms(struct intel_dp *intel_dp, int mode)
{
- uint32_t dp_reg = io_i915_read32(intel_dp->output_reg);
+ uint32_t dp_reg = gtt_read(intel_dp->output_reg);
printk(BIOS_SPEW, "%s: power %s\n", __func__, mode ? "off" : "on");
if (mode){
@@ -1402,7 +1402,7 @@
printk(BIOS_SPEW, "%s: dp_reg_value %08lx dp_train_pat %02x\n",
__func__, (unsigned long) dp_reg_value, dp_train_pat);
if (intel_dp->is_haswell){
- temp = io_i915_read32(DP_TP_CTL(port));
+ temp = gtt_read(DP_TP_CTL(port));
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
@@ -1413,11 +1413,11 @@
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
case DP_TRAINING_PATTERN_DISABLE:
temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
- io_i915_write32( temp, DP_TP_CTL(port));
+ gtt_write(DP_TP_CTL(port), temp);
for(i = 0; i < 10; i++){
u32 status;
- status = io_i915_read32(DP_TP_STATUS(port));
+ status = gtt_read(DP_TP_STATUS(port));
if (status & DP_TP_STATUS_IDLE_DONE)
break;
}
@@ -1440,7 +1440,7 @@
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
break;
}
- io_i915_write32( temp, DP_TP_CTL(port));
+ gtt_write(DP_TP_CTL(port), temp);
} else if (intel_dp->has_pch_cpt &&
(intel_dp->gen != 7 || !is_cpu_edp(intel_dp))) {
@@ -1483,7 +1483,7 @@
}
}
- io_i915_write32( dp_reg_value, intel_dp->output_reg);
+ gtt_write(intel_dp->output_reg, dp_reg_value);
//POSTING_READ(intel_dp->output_reg);
intel_dp_aux_native_write_1(intel_dp,
@@ -1702,7 +1702,7 @@
++tries;
}
- //io_i915_write32(reg, intel_dp->output_reg);
+ //gtt_write(intel_dp->output_reg,reg);
////POSTING_READ(intel_dp->output_reg);
intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
}
@@ -1712,7 +1712,7 @@
{
uint32_t DP = intel_dp->DP;
- if ((io_i915_read32(intel_dp->output_reg) & DP_PORT_EN) == 0)
+ if ((gtt_read(intel_dp->output_reg) & DP_PORT_EN) == 0)
return;
if (intel_dp->is_haswell){
@@ -1721,17 +1721,17 @@
}
if (is_edp(intel_dp)) {
DP &= ~DP_PLL_ENABLE;
- io_i915_write32(DP, intel_dp->output_reg);
+ gtt_write(intel_dp->output_reg,DP);
////POSTING_READ(intel_dp->output_reg);
udelay(100);
}
if (intel_dp->has_pch_cpt && ((intel_dp->gen == 7) || !is_cpu_edp(intel_dp))) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
- io_i915_write32(DP | DP_LINK_TRAIN_PAT_IDLE_CPT, intel_dp->output_reg);
+ gtt_write(intel_dp->output_reg,DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
} else {
DP &= ~DP_LINK_TRAIN_MASK;
- io_i915_write32(DP | DP_LINK_TRAIN_PAT_IDLE, intel_dp->output_reg);
+ gtt_write(intel_dp->output_reg,DP | DP_LINK_TRAIN_PAT_IDLE);
}
////POSTING_READ(intel_dp->output_reg);
@@ -1745,7 +1745,7 @@
}
DP &= ~DP_AUDIO_OUTPUT_ENABLE;
- io_i915_write32(DP & ~DP_PORT_EN, intel_dp->output_reg);
+ gtt_write(intel_dp->output_reg,DP & ~DP_PORT_EN);
////POSTING_READ(intel_dp->output_reg);
mdelay(600000); //intel_dp->panel_power_down_delay);
}
@@ -1793,25 +1793,25 @@
void intel_dp_set_m_n_regs(struct intel_dp *intel_dp)
{
- io_i915_write32(0x7e4a0000, PIPE_DATA_M1(intel_dp->transcoder));
- /* io_i915_write32(0x00800000,0x6f034); */
+ gtt_write(PIPE_DATA_M1(intel_dp->transcoder),0x7e4a0000);
+ /* gtt_write(0x6f034,0x00800000); */
/* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
However, with our formula we always see values 0x7e43yyyy (1366 panel) and
0x7e42yyy (1280 panel) */
- /* io_i915_write32(TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m,PIPE_DATA_M1(intel_dp->transcoder)); */
- io_i915_write32(intel_dp->m_n.gmch_n, PIPE_DATA_N1(intel_dp->transcoder));
- io_i915_write32(intel_dp->m_n.link_m, PIPE_LINK_M1(intel_dp->transcoder));
- io_i915_write32(intel_dp->m_n.link_n, PIPE_LINK_N1(intel_dp->transcoder));
+ /* gtt_write(PIPE_DATA_M1(intel_dp->transcoder),TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m); */
+ gtt_write(PIPE_DATA_N1(intel_dp->transcoder),intel_dp->m_n.gmch_n);
+ gtt_write(PIPE_LINK_M1(intel_dp->transcoder),intel_dp->m_n.link_m);
+ gtt_write(PIPE_LINK_N1(intel_dp->transcoder),intel_dp->m_n.link_n);
}
void intel_dp_set_resolution(struct intel_dp *intel_dp)
{
- io_i915_write32(intel_dp->htotal, HTOTAL(intel_dp->transcoder));
- io_i915_write32(intel_dp->hblank, HBLANK(intel_dp->transcoder));
- io_i915_write32(intel_dp->hsync, HSYNC(intel_dp->transcoder));
- io_i915_write32(intel_dp->vtotal, VTOTAL(intel_dp->transcoder));
- io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder));
- io_i915_write32(intel_dp->vsync, VSYNC(intel_dp->transcoder));
+ gtt_write(HTOTAL(intel_dp->transcoder),intel_dp->htotal);
+ gtt_write(HBLANK(intel_dp->transcoder),intel_dp->hblank);
+ gtt_write(HSYNC(intel_dp->transcoder),intel_dp->hsync);
+ gtt_write(VTOTAL(intel_dp->transcoder),intel_dp->vtotal);
+ gtt_write(VBLANK(intel_dp->transcoder),intel_dp->vblank);
+ gtt_write(VSYNC(intel_dp->transcoder),intel_dp->vsync);
}
int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 4b002ec..7c95e40 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -87,33 +87,13 @@
static unsigned int *mmio;
static unsigned int graphics;
-static unsigned short addrport;
-static unsigned short dataport;
static unsigned int physbase;
-static int ioread = 0, iowrite = 0;
-
void ug1(int);
void ug2(int);
void ug22(int);
void ug3(int);
-unsigned long io_i915_read32(unsigned long addr)
-{
- unsigned long val;
- outl(addr, addrport);
- val = inl(dataport);
- ioread += 2;
- return val;
-}
-
-void io_i915_write32(unsigned long val, unsigned long addr)
-{
- outl(addr, addrport);
- outl(val, dataport);
- iowrite += 2;
-}
-
/* GTT is the Global Translation Table for the graphics pipeline.
* It is used to translate graphics addresses to physical
* memory addresses. As in the CPU, GTTs map 4K pages.
@@ -133,6 +113,8 @@
* starting at physbase.
*/
+#define GTT_PTE_BASE (2 << 20)
+
static void
setgtt(int start, int end, unsigned long base, int inc)
{
@@ -144,7 +126,8 @@
* the values that mrc does no
* useful setup before we run this.
*/
- io_i915_write32(word|1,(i*4)|1);
+ gtt_write(GTT_PTE_BASE + i * 4, word|1);
+ gtt_read(GTT_PTE_BASE + i * 4);
}
}
@@ -157,7 +140,7 @@
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
- io_i915_write32(color, _LGC_PALETTE_A + (i<<2));
+ gtt_write(_LGC_PALETTE_A + (i<<2),color);
}
}
@@ -251,8 +234,8 @@
u8 read_val;
u8 link_status[DP_LINK_STATUS_SIZE];
- io_i915_write32(0x80040000,DP_TP_CTL_A);
- io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
+ gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
intel_dp_get_training_pattern(intel_dp, &read_val);
intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
@@ -260,7 +243,7 @@
intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
intel_dp_get_link_status(intel_dp, link_status);
- io_i915_write32(0x80040100,DP_TP_CTL_A);
+ gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
intel_dp_get_training_pattern(intel_dp, &read_val);
intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
@@ -270,34 +253,54 @@
intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
}
-int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
- unsigned int gfx, unsigned int init_fb);
-int i915lightup(unsigned int pphysbase, unsigned int piobase,
- unsigned int pmmio, unsigned int pgfx, unsigned int init_fb)
+#define TEST_GFX 0
+
+#if TEST_GFX
+static void test_gfx(struct intel_dp *dp)
+{
+ int i;
+
+ /* This is a sanity test code which fills the screen with two bands --
+ green and blue. It is very useful to ensure all the initializations
+ are made right. Thus, to be used only for testing, not otherwise
+ */
+ for (i = 0; i < (dp->edid.va - 4); i++) {
+ u32 *l;
+ int j;
+ u32 tcolor = 0x0ff;
+ for (j = 0; j < (dp->edid.ha-4); j++) {
+ if (j == (dp->edid.ha/2)) {
+ tcolor = 0xff00;
+ }
+ l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+ memcpy(l,&tcolor,sizeof(tcolor));
+ }
+ }
+}
+#else
+static void test_gfx(struct intel_dp *dp) {}
+#endif
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+ unsigned int pgfx, unsigned int init_fb)
{
int must_cycle_power = 0;
struct intel_dp adp, *dp = &adp;
- /* frame buffer pointer */
- /* u32 *l; */
int i;
int edid_ok;
- /* u32 tcolor = 0xff; */
int pixels = FRAME_BUFFER_BYTES/64;
mmio = (void *)pmmio;
- addrport = piobase;
- dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p"
- "addrport %04x physbase %08x\n",
- (void *)graphics, mmio, addrport, physbase);
+ "physbase %08x\n",
+ (void *)graphics, mmio, physbase);
void runio(struct intel_dp *dp);
void runlinux(struct intel_dp *dp);
-
- dp->gen = 8; // ??
+ dp->gen = 8; // This is gen 8 which we believe is Haswell
dp->is_haswell = 1;
dp->DP = 0x2;
/* These values are used for training the link */
@@ -308,6 +311,7 @@
dp->panel_power_cycle_delay = 600;
dp->pipe = PIPE_A;
dp->port = PORT_A;
+ dp->plane = PLANE_A;
dp->clock = 160000;
dp->bpp = 32;
dp->type = INTEL_OUTPUT_EDP;
@@ -327,8 +331,6 @@
memset((void*)graphics, 0, 4096);
}
- //intel_prepare_ddi_buffers(0, 0);
- //ironlake_edp_panel_vdd_on(dp);
dp->address = 0x50;
if ( !intel_dp_get_dpcd(dp) )
@@ -351,9 +353,7 @@
dp_init_dim_regs(dp);
- /* more undocumented stuff. */
- /* possibly not even needed. */
- io_i915_write32(0x00000021,0x6f410);
+ intel_ddi_set_pipe_settings(dp);
runio(dp);
@@ -362,31 +362,19 @@
pixels = dp->edid.ha * (dp->edid.va-4) * 4;
printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
- /* for (i = 0; i < (dp->edid.va - 4); i++) { */
- /* int j; */
- /* tcolor = 0x0ff; */
- /* for (j = 0; j < (dp->edid.ha-4); j++) { */
- /* if (j == (dp->edid.ha/2)) { */
- /* tcolor = 0xff00; */
- /* } */
- /* l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); */
- /* memcpy(l,&tcolor,sizeof(tcolor)); */
- /* } */
- /* } */
+ test_gfx(dp);
set_vbe_mode_info_valid(&dp->edid, graphics);
i915_init_done = 1;
- //io_i915_write32( 0x80000000,BLC_PWM_CPU_CTL2);
- //io_i915_write32( 0x80000000,BLC_PWM_PCH_CTL1);
return i915_init_done;
fail:
printk(BIOS_SPEW, "Graphics could not be started;");
if (0 && must_cycle_power){
printk(BIOS_SPEW, "Turn off power and wait ...");
- io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,0xabcd0000);
udelay(600000);
- io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
}
printk(BIOS_SPEW, "Returning.\n");
return 0;
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index 0801122..7fbffb6 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -47,34 +47,17 @@
/* vbios spins at this point. Some haswell weirdness? */
intel_dp_wait_panel_power_control(0xabcd0008);
- /* This is stuff we don't totally understand yet. */
- io_i915_write32(0x03a903a9,BLC_PWM_CPU_CTL);
- io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
- io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
- io_i915_write32(0x00ffffff,0x64ea8);
- io_i915_write32(0x00040006,0x64eac);
- io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
- io_i915_write32(0x80000000,0x45400);
- intel_dp_wait_reg(0x00045400, 0xc0000000);
- io_i915_write32(0x8000298e,CPU_VGACNTRL);
- io_i915_write32(0x00000000,_CURACNTR);
- io_i915_write32(0x00000000,_CURABASE);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32(0x00000000,_CURBCNTR_IVB);
- io_i915_write32(0x00000000,_CURBBASE_IVB);
- io_i915_write32(0x00000000,_DSPBCNTR);
- io_i915_write32(0x00000000,_DSPBSURF);
- io_i915_write32(0x00000000,0x72080);
- io_i915_write32(0x00000000,0x72084);
- io_i915_write32(0x00000000,_DVSACNTR);
- io_i915_write32(0x00000000,_DVSASURF);
- io_i915_write32(0x00008000,DEIIR);
- intel_dp_wait_reg(0x00044008, 0x00000000);
- io_i915_write32(0x8020298e,CPU_VGACNTRL);
- io_i915_write32(/*0x00000800*/dp->stride,_DSPASTRIDE);
- io_i915_write32(0x00000000,_DSPAADDR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
+ /* This should be a function like intel_panel_enable_backlight
+ However, we are not sure how the value 0x3a9 comes up.
+ It has to do something with PWM frequency */
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
+
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
intel_dp_sink_dpms(dp, 0);
@@ -83,25 +66,18 @@
intel_dp_set_m_n_regs(dp);
intel_dp_set_resolution(dp);
- io_i915_write32(dp->pipesrc,PIPESRC(dp->pipe));
- io_i915_write32(0x00000000, PIPECONF(dp->transcoder));
- io_i915_write32(0x00000000, PCH_TRANSCONF(dp->pipe));
- io_i915_write32(0x20000000,PORT_CLK_SEL_A);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);
- io_i915_write32(dp->stride,_DSPASTRIDE);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+ gtt_write(PIPECONF(dp->transcoder),0x00000000);
+ gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
- io_i915_write32(0x00000000,_DSPAADDR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32(0x00000080,DEIIR);
+ gtt_write(PORT_CLK_SEL(dp->port),PORT_CLK_SEL_LCPLL_1350);
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+ gtt_write(DEIIR,0x00000080);
- io_i915_write32(0x00230000,TRANS_DDI_FUNC_CTL_EDP);
- io_i915_write32(0x00000010,0x7f008);
- io_i915_write32(dp->flags,TRANS_DDI_FUNC_CTL_EDP);
- io_i915_write32(0x80000010,0x7f008);
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+ gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
intel_dp_wait_panel_power_control(0xabcd000a);
@@ -114,14 +90,13 @@
intel_dp_i2c_read(dp, &read_val);
/* this needs to be a call to a function */
- io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
- io_i915_write32(0x00000001,TRANS_DDI_FUNC_CTL_EDP+0x10);
- io_i915_write32(0x80040011,DP_TP_CTL_A);
- io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091,DP_A);
+ gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
- io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a,PCH_PP_ON_DELAYS);
- io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a,PCH_PP_ON_DELAYS);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
intel_dp_set_bw(dp);
intel_dp_set_lane_count(dp);
@@ -129,69 +104,33 @@
mainboard_train_link(dp);
/* need a function: intel_ddi_set_tp or similar */
- io_i915_write32(0x80040200,DP_TP_CTL_A);
- io_i915_write32(0x80040300,DP_TP_CTL_A);
- io_i915_write32(0x03a903a9,BLC_PWM_CPU_CTL);
- io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
- io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
/* some of this is not needed. */
- io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
- io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
- io_i915_write32(0x00000000,SDEIIR);
- io_i915_write32(0x00000000,SDEIIR);
- io_i915_write32(0x00000000,DEIIR);
- io_i915_write32(0x80000000,0x45400);
- intel_dp_wait_reg(0x00045400, 0xc0000000);
- io_i915_write32(0x80000000,0x45400);
- intel_dp_wait_reg(0x00045400, 0xc0000000);
- printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x6)");
- io_i915_write32(0x80000000,0x45400);
- intel_dp_wait_reg(0x00045400, 0xc0000000);
- io_i915_write32(0x8000298e,CPU_VGACNTRL);
- io_i915_write32(0x00000000,_CURACNTR);
- io_i915_write32(0x00000000,_CURABASE);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32(0x00000000,_CURBCNTR_IVB);
- io_i915_write32(0x00000000,_CURBBASE_IVB);
- io_i915_write32(0x00000000,_DSPBCNTR);
- io_i915_write32(0x00000000,_DSPBSURF);
- io_i915_write32(0x00000000,0x72080);
- io_i915_write32(0x00000000,0x72084);
- io_i915_write32(0x00000000,_DVSACNTR);
- io_i915_write32(0x00000000,_DVSASURF);
- io_i915_write32(0x00008000,DEIIR);
- intel_dp_wait_reg(0x00044008, 0x00000000);
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
- /* we just turned vdd off. We're not going to wait. The panel is up. */
- io_i915_write32(0x8020298e,CPU_VGACNTRL);
- io_i915_write32(/*0x00000640*/dp->stride,_DSPASTRIDE);
- io_i915_write32(0x00000000,_DSPAADDR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- /* io_i915_write32(dp->pfa_pos,_PFA_WIN_POS); */
- /* io_i915_write32(0x00000000,_PFA_WIN_SZ); */
- io_i915_write32(dp->pipesrc,_PIPEASRC);
- /* io_i915_write32(dp->pfa_pos,_PFA_WIN_POS); */
- /* io_i915_write32(dp->pfa_ctl,_PFA_CTL_1); */
- /* io_i915_write32(dp->pfa_sz,_PFA_WIN_SZ); */
- io_i915_write32(0x00000080,DEIIR);
- intel_dp_wait_reg(0x00044008, 0x00000000);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);
- io_i915_write32(/*0x00000640*/dp->stride,_DSPASTRIDE);
- io_i915_write32(0x00000000,_DSPAADDR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
- io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x98000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
- io_i915_write32( EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON |0x00000007,PCH_PP_CONTROL);
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
- io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
- io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
- io_i915_write32(0x00000000,SDEIIR);
- io_i915_write32(0x00000000,SDEIIR);
- io_i915_write32(0x00000000,DEIIR);
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+ gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
}
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e06db75..44ee718 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -24,6 +24,8 @@
select REQUIRES_BLOB
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
+ select INTEL_DDI
+ select INTEL_DP
if NORTHBRIDGE_INTEL_HASWELL
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index ee447bfc..9dfba9a 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -25,7 +25,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/gma/i915_reg.h>
+#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
+#include <stdlib.h>
#include "chip.h"
#include "haswell.h"
@@ -126,12 +128,12 @@
static struct resource *gtt_res = NULL;
-static inline u32 gtt_read(u32 reg)
+u32 gtt_read(u32 reg)
{
return read32(gtt_res->base + reg);
}
-static inline void gtt_write(u32 reg, u32 data)
+void gtt_write(u32 reg, u32 data)
{
write32(gtt_res->base + reg, data);
}
@@ -209,7 +211,10 @@
gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Enable PM Interrupts */
- gtt_write(0x4402c, 0x03000076);
+ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |
+ GEN6_PM_RP_DOWN_TIMEOUT | GEN6_PM_RP_UP_THRESHOLD |
+ GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_UP_EI_EXPIRED |
+ GEN6_PM_RP_DOWN_EI_EXPIRED);
/* Enable RC6 in idle */
gtt_write(0x0a094, 0x00040000);
@@ -218,6 +223,26 @@
gtt_write_regs(haswell_gt_lock);
}
+static void init_display_planes(void)
+{
+ int pipe, plane;
+
+ /* Disable cursor mode */
+ for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
+ gtt_write(CURCNTR_IVB(pipe), CURSOR_MODE_DISABLE);
+ gtt_write(CURBASE_IVB(pipe), 0x00000000);
+ }
+
+ /* Disable primary plane and set surface base address*/
+ for (plane = PLANE_A; plane <= PLANE_C; plane++) {
+ gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE);
+ gtt_write(DSPSURF(plane), 0x00000000);
+ }
+
+ /* Disable VGA display */
+ gtt_write(CPU_VGACNTRL, CPU_VGA_DISABLE);
+}
+
static void gma_setup_panel(struct device *dev)
{
struct northbridge_intel_haswell_config *conf = dev->chip_info;
@@ -226,122 +251,90 @@
printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
/* Setup Digital Port Hotplug */
- reg32 = gtt_read(0xc4030);
+ reg32 = gtt_read(PCH_PORT_HOTPLUG);
if (!reg32) {
reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
- gtt_write(0xc4030, reg32);
+ gtt_write(PCH_PORT_HOTPLUG, reg32);
}
/* Setup Panel Power On Delays */
- reg32 = gtt_read(0xc7208);
+ reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
- gtt_write(0xc7208, reg32);
+ gtt_write(PCH_PP_ON_DELAYS, reg32);
}
/* Setup Panel Power Off Delays */
- reg32 = gtt_read(0xc720c);
+ reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) {
reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
- gtt_write(0xc720c, reg32);
+ gtt_write(PCH_PP_OFF_DELAYS, reg32);
}
/* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) {
- reg32 = gtt_read(0xc7210);
+ reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0xff;
reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
- gtt_write(0xc7210, reg32);
+ gtt_write(PCH_PP_DIVISOR, reg32);
}
/* Enable Backlight if needed */
if (conf->gpu_cpu_backlight) {
- gtt_write(0x48250, (1 << 31));
- gtt_write(0x48254, conf->gpu_cpu_backlight);
+ gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
+ gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight);
}
if (conf->gpu_pch_backlight) {
- gtt_write(0xc8250, (1 << 31));
- gtt_write(0xc8254, conf->gpu_pch_backlight);
+ gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
+ gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight);
}
/* Get display,pipeline,and DDI registers into a basic sane state */
- /* not all these have documented names. */
- gtt_write(0x45400, 0x80000000);
- gtt_poll( 0x00045400, 0xc0000000, 0xc0000000);
- gtt_write(_CURACNTR, 0x00000000);
- gtt_write(_DSPACNTR, (/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000);
- gtt_write(_DSPBCNTR, 0x00000000);
- gtt_write(CPU_VGACNTRL, 0x8000298e);
- gtt_write(_DSPASIZE+0xc, 0x00000000);
- gtt_write(_DSPBSURF, 0x00000000);
- gtt_write(0x4f008, 0x00000000);
- gtt_write(0x4f008, 0x00000000);
- gtt_write(0x4f008, 0x00000000);
- gtt_write(0x4f040, 0x01000001);
- gtt_write(0x4f044, 0x00000000);
- gtt_write(0x4f048, 0x00000000);
- gtt_write(0x4f04c, 0x03030000);
- gtt_write(0x4f050, 0x00000000);
- gtt_write(0x4f054, 0x00000001);
- gtt_write(0x4f058, 0x00000000);
- gtt_write(0x4f04c, 0x03450000);
- gtt_write(0x4f04c, 0x45450000);
- gtt_write(0x4f000, 0x03000400);
- gtt_write(DP_A, 0x00000091); /* DDI-A enable */
+ power_well_enable();
+
+ init_display_planes();
+
+ /* DDI-A params set:
+ bit 0: Display detected (RO)
+ bit 4: DDI A supports 4 lanes and DDI E is not used
+ bit 7: DDI buffer is idle
+ */
+ gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED);
+
+ /* Set FDI registers - is this required? */
gtt_write(_FDI_RXA_MISC, 0x00200090);
gtt_write(_FDI_RXA_MISC, 0x0a000000);
- gtt_write(0x46408, 0x00000070);
+
+ /* Enable the handshake with PCH display when processing reset */
+ gtt_write(NDE_RSTWRN_OPT, RST_PCH_HNDSHK_EN);
+
+ /* undocumented */
gtt_write(0x42090, 0x04000000);
- gtt_write(0x4f050, 0xc0000000);
gtt_write(0x9840, 0x00000000);
gtt_write(0x42090, 0xa4000000);
- gtt_write(SOUTH_DSPCLK_GATE_D, 0x00001000);
+
+ gtt_write(SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE);
+
+ /* undocumented */
gtt_write(0x42080, 0x00004000);
- gtt_write(0x64f80, 0x00ffffff);
- gtt_write(0x64f84, 0x0007000e);
- gtt_write(0x64f88, 0x00d75fff);
- gtt_write(0x64f8c, 0x000f000a);
- gtt_write(0x64f90, 0x00c30fff);
- gtt_write(0x64f94, 0x00060006);
- gtt_write(0x64f98, 0x00aaafff);
- gtt_write(0x64f9c, 0x001e0000);
- gtt_write(0x64fa0, 0x00ffffff);
- gtt_write(0x64fa4, 0x000f000a);
- gtt_write(0x64fa8, 0x00d75fff);
- gtt_write(0x64fac, 0x00160004);
- gtt_write(0x64fb0, 0x00c30fff);
- gtt_write(0x64fb4, 0x001e0000);
- gtt_write(0x64fb8, 0x00ffffff);
- gtt_write(0x64fbc, 0x00060006);
- gtt_write(0x64fc0, 0x00d75fff);
- gtt_write(0x64fc4, 0x001e0000);
- gtt_write(DDI_BUF_TRANS_A, 0x00ffffff);
- gtt_write(DDI_BUF_TRANS_A+0x4, 0x0006000e);
- gtt_write(DDI_BUF_TRANS_A+0x8, 0x00d75fff);
- gtt_write(DDI_BUF_TRANS_A+0xc, 0x0005000a);
- gtt_write(DDI_BUF_TRANS_A+0x10, 0x00c30fff);
- gtt_write(DDI_BUF_TRANS_A+0x14, 0x00040006);
- gtt_write(DDI_BUF_TRANS_A+0x18, 0x80aaafff);
- gtt_write(DDI_BUF_TRANS_A+0x1c, 0x000b0000);
- gtt_write(DDI_BUF_TRANS_A+0x20, 0x00ffffff);
- gtt_write(DDI_BUF_TRANS_A+0x24, 0x0005000a);
- gtt_write(DDI_BUF_TRANS_A+0x28, 0x00d75fff);
- gtt_write(DDI_BUF_TRANS_A+0x2c, 0x000c0004);
- gtt_write(DDI_BUF_TRANS_A+0x30, 0x80c30fff);
- gtt_write(DDI_BUF_TRANS_A+0x34, 0x000b0000);
- gtt_write(DDI_BUF_TRANS_A+0x38, 0x00ffffff);
- gtt_write(DDI_BUF_TRANS_A+0x3c, 0x00040006);
- gtt_write(DDI_BUF_TRANS_A+0x40, 0x80d75fff);
- gtt_write(DDI_BUF_TRANS_A+0x44, 0x000b0000);
- gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL,
- DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010);
- gtt_write(SDEISR+0x30,
- PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010);
+
+ /* Prepare DDI buffers for DP and FDI */
+ intel_prepare_ddi();
+
+ /* Hot plug detect buffer enabled for port A */
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE);
+
+ /* Enable HPD buffer for digital port D and B */
+ gtt_write(PCH_PORT_HOTPLUG, PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE);
+
+ /* Bits 4:0 - Power cycle delay (default 0x6 --> 500ms)
+ Bits 31:8 - Reference divider (0x0004af ----> 24MHz)
+ */
gtt_write(PCH_PP_DIVISOR, 0x0004af06);
}
@@ -406,19 +399,16 @@
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
- u32 iobase, mmiobase, physbase;
+ u32 mmiobase, physbase;
/* Default set to 1 since it might be required for
stuff like seabios */
unsigned int init_fb = 1;
- iobase = dev->resource_list[2].base;
mmiobase = dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
#ifdef CONFIG_CHROMEOS
init_fb = developer_mode_enabled() || recovery_mode_enabled();
#endif
- int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
- unsigned int gfx, unsigned int init_fb);
- lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base, init_fb);
+ lightup_ok = i915lightup(physbase, mmiobase, graphics_base, init_fb);
if (lightup_ok)
gfx_set_init_done(1);
#endif
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 2470b0f..f76fbc4 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -272,12 +272,12 @@
static struct resource *gtt_res = NULL;
-static inline u32 gtt_read(u32 reg)
+u32 gtt_read(u32 reg)
{
return read32(gtt_res->base + reg);
}
-static inline void gtt_write(u32 reg, u32 data)
+void gtt_write(u32 reg, u32 data)
{
write32(gtt_res->base + reg, data);
}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 0add055..f305b81 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -595,7 +595,7 @@
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
- int lightup_ok = i915lightup(conf, physbase, iobase, mmiobase, graphics_base);
+ int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base);
if (lightup_ok)
gfx_set_init_done(1);
#endif
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index bc5d986..b7502cd 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -168,5 +168,5 @@
struct northbridge_intel_sandybridge_config;
-int i915lightup(const struct northbridge_intel_sandybridge_config *info,
+int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
u32 physbase, u16 pio, u32 mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index ff877ff..53fbfda 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -207,7 +207,7 @@
read32(mmio + 0xc4000);
}
-int i915lightup(const struct northbridge_intel_sandybridge_config *info,
+int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
u32 physbase, u16 piobase, u32 mmio, u32 lfb)
{
int i;