commit 77757c22b9eede92234d07d65a23fdf4b970c8cf
author Edward O'Callaghan <eocallaghan@alterapraxis.com> Sun Jan 04 21:33:39 2015 +1100
committer Edward O'Callaghan <eocallaghan@alterapraxis.com> Tue Jan 06 01:51:42 2015 +0100
tree 29949ed8cfac9c5c9b2cf4c8071c74690411d32d
parent d76ac6349df0147b9d8f7f09f8bb80343ecfb5e6

mainboard/*/romstage.c: Sanitize system header inclusions

Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/mainboard/msi/ms9652_fam10/romstage.c

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 722122d..9cc3640 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -34,14 +34,14 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
-#include "northbridge/amd/amdfam10/raminit.h"
-#include "northbridge/amd/amdfam10/amdfam10.h"
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 #include "lib/delay.c"
-#include "cpu/x86/lapic.h"
+#include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/nvidia/mcp55/early_ctrl.c"
@@ -55,7 +55,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdfam10/amdfam10.h"
+#include <northbridge/amd/amdfam10/amdfam10.h>
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
@@ -69,9 +69,9 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include <southbridge/nvidia/mcp55/early_setup_ss.h>
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/microcode.h"
+#include <cpu/amd/microcode.h>
 
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"