diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index 0cc46a6..24d3813 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -28,6 +28,35 @@
 #include <arch/ioapic.h>
 #include "i82371eb.h"
 
+static void enable_intel_82093aa_ioapic(void)
+{
+	u16 reg16;
+	u32 reg32;
+	u8 ioapic_id = 2;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
+
+	/* Enable IOAPIC. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= (1 << 8); /* APIC Chip Select */
+	pci_write_config16(dev, XBCS, reg16);
+
+	/* Set the IOAPIC ID. */
+	*ioapic_index = 0;
+	*ioapic_data = ioapic_id << 24;
+
+	/* Read back and verify the IOAPIC ID. */
+	*ioapic_index = 0;
+	reg32 = (*ioapic_data >> 24) & 0x0f;
+	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+	if (reg32 != ioapic_id)
+		die("IOAPIC error!\n");
+}
+
 static void isa_init(struct device *dev)
 {
 	u32 reg32;
@@ -45,6 +74,18 @@
 
 	/* Initialize ISA DMA. */
 	isa_dma_init();
+
+#if CONFIG_IOAPIC
+	/*
+	 * Unlike most other southbridges the 82371EB doesn't have a built-in
+	 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
+	 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
+	 *
+	 * Thus, we can/must only enable the IOAPIC if it actually exists,
+	 * i.e. the respective mainboard does "select IOAPIC".
+	 */
+	enable_intel_82093aa_ioapic();
+#endif
 }
 
 static void sb_read_resources(struct device *dev)