Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D.
- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
Intel 82371EB southbridge (sets the proper chip-select) and sets an
IOAPIC ID.
- We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
as on 82371EB-based boards the IOAPIC is an external chip (not integrated
in the southbridge) and it's only populated on multi-CPU boards.
That is, we cannot unconditionally enable it, only on SMP-capable boards.
- Due to the reason explained above, remove "select IOAPIC" from
src/southbridge/intel/i82371eb/Kconfig, and add it to
src/mainboard/asus/p2b-d/Kconfig.
- Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
- Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
are set.
- Rework ASUS P2B-D mptable.c to fix a number of things:
- Convert it to use mptable_write_buses() as all mptable.c files should do.
- Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).
- Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
On Linux I now get two entries in /proc/cpuinfo (where only one appeared
before this patch), i.e. both populated CPUs are found.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 12ca789..699cbea 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -27,6 +27,7 @@
static void *smp_write_config_table(void *v)
{
+ int ioapic_id, ioapic_ver, isa_bus;
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -35,13 +36,12 @@
smp_write_processors(mc);
- /* Bus: Bus ID Type */
- smp_write_bus(mc, 0, "PCI ");
- smp_write_bus(mc, 1, "PCI ");
- smp_write_bus(mc, 2, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ ioapic_id = 2;
+ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+
{
device_t dev;
struct resource *res;
@@ -49,45 +49,39 @@
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
- smp_write_ioapic(mc, 3, 0x20, res->base);
+ smp_write_ioapic(mc, 3, ioapic_ver, res->base);
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
- smp_write_ioapic(mc, 4, 0x20, res->base);
+ smp_write_ioapic(mc, 4, ioapic_ver, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
- smp_write_ioapic(mc, 5, 0x20, res->base);
+ smp_write_ioapic(mc, 5, ioapic_ver, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
- smp_write_ioapic(mc, 8, 0x20, res->base);
+ smp_write_ioapic(mc, 8, ioapic_ver, res->base);
}
}
- mptable_add_isa_interrupts(mc, 0x2, 0x2, 0);
+ /* Legacy Interrupts */
+ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- 0x2, 0xb, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- 0x2, 0xa, 0x2, 0x13);
+ /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_lintsrc(mc, mp_ExtINT,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0,
- MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
- 0x2, 0x0, MP_APIC_ALL, 0x1);
+ /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
+ /* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);