soc/intel/adl: Option to create unified AP FW for UFS/Non-UFS SKUs
This patch makes it easy for OEMs to keep a unified AP firmware image
to boot different SKUs with UFS and non-UFS as boot media.
With a unified image while booting on non-UFS SKU is exhibiting S0ix
failure due to UFS remain enabled in the strap although FSP-S is
making the UFS controller function disabled.
The potential root cause of this behaviour is although the UFS
controller is function disabled but MPHY clock is still in active
state.
A possible solution to this problem is to issue a warm reboot (if
boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC
read the function disable state of the UFS for disabling the MPHY
clock.
Mainboard users with such board design where OEM would like to use
an unified AP firmware to support both UFS and non-UFS sku booting
might need to choose this config to allow disabling UFS while booting
on the non-UFS SKU.
Note: selection of this config would introduce an additional warm
reset in cold-reset scenarios due to function disabling of the UFS
controller.
BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a200121..5e3209a 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -447,6 +447,28 @@
help
Selects the workarounds applicable for Alder Lake SoC.
+config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+ bool
+ help
+ Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an
+ unified AP firmware which demanded to have a unified descriptor. It means UFS
+ controller needs to default fuse enabled to let UFS SKU to boot.
+
+ On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain
+ enabled in the strap although FSP-S is making the UFS controller function
+ disabled. The potential root cause of this behaviour is although the UFS
+ controller is function disabled but MPHY clock is still in active state.
+
+ A possible solution to this problem is to issue a warm reboot (if boot path is
+ S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function
+ disable state of the UFS for disabling the MPHY clock.
+
+ Mainboard users with such board design where OEM would like to use an unified AP
+ firmware to support both UFS and non-UFS sku booting might need to choose this
+ config to allow disabling UFS while booting on the non-UFS SKU.
+ Note: selection of this config would introduce an additional warm reset in
+ cold-reset scenarios due to function disabling of the UFS controller.
+
choice
prompt "Multiprocessor (MP) Initialization configuration to use"
default USE_FSP_MP_INIT