acpi: Move ACPI table support out of arch/x86 (3/5)
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 03230a5..e894466 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <stdint.h>
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index bdd0ed0..c81d21f 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -3,8 +3,8 @@
#include <types.h>
#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 5f6c8a1..d566120 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -8,7 +8,7 @@
#include <stdint.h>
#include <device/device.h>
#include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <cpu/intel/smm_reloc.h>
#include "chip.h"
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 5b68a73..9bfb4e9 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -5,7 +5,7 @@
#include <romstage_handoff.h>
#include <console/console.h>
#include <device/pci_ops.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <cpu/x86/lapic.h>
#include <arch/romstage.h>
#include <northbridge/intel/gm45/gm45.h>
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f4d9d65..a66847d 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -3,7 +3,7 @@
#include <types.h>
#include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index f7c6883..552f032 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -3,7 +3,7 @@
#include <commonlib/helpers.h>
#include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/haswell/haswell.h>
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index e1258e0..1c7eabc 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -2,8 +2,8 @@
/* This file is part of the coreboot project. */
#include <types.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "i945.h"
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 3fd3db6..c080d0c 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -8,7 +8,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <cpu/intel/smm_reloc.h>
#include "i945.h"
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index c1ee207..7384223 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -2,7 +2,7 @@
/* This file is part of the coreboot project. */
#include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c
index 54c42cf..cf91f1e 100644
--- a/src/northbridge/intel/pineview/acpi.c
+++ b/src/northbridge/intel/pineview/acpi.c
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
-#include <arch/acpigen.h>
-#include <arch/acpi.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi.h>
#include <device/device.h>
#include <northbridge/intel/pineview/pineview.h>
#include <types.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index b243563..af4bfb8 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -8,7 +8,7 @@
#include <stdint.h>
#include <device/device.h>
#include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <northbridge/intel/pineview/pineview.h>
#include <cpu/intel/smm_reloc.h>
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 77aa8149..3ae44b8 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -4,7 +4,7 @@
#include <types.h>
#include <console/console.h>
#include <commonlib/helpers.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ea2a737..e947bc5 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -2,7 +2,7 @@
/* This file is part of the coreboot project. */
#include <console/console.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c
index fb1ebab..67fc933 100644
--- a/src/northbridge/intel/x4x/acpi.c
+++ b/src/northbridge/intel/x4x/acpi.c
@@ -3,8 +3,8 @@
#include <types.h>
#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <device/device.h>
#include "x4x.h"
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 054d2aa..8aab1f6 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -8,7 +8,7 @@
#include <stdint.h>
#include <device/device.h>
#include <boot/tables.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
#include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/chip.h>
#include <northbridge/intel/x4x/x4x.h>