soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD
The Kconfig is only used in common code to gather the build time
maximum socket number FSP support. The same information is available
in FSP header as MAX_SOCKET, thus use the FSP as truth of source.
Currently MAX_SOCKET is 4.
Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 832aab5..15b915d 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -27,14 +27,6 @@
string
default "\\_SB.C%03X"
-config MAX_SOCKET_UPD
- int
- default 2
- help
- This is used for configuring common SPR UPD tables which their sizes
- depend on the socket number. Since it's the maximal socket number for
- the common UPD tables, mainboard should not overwrite it.
-
config SIPI_FINAL_TIMEOUT
int
default 400000
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index aacc3ab..f36e5cc 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -23,8 +23,8 @@
#include "chip.h"
/* Initialize to all zero first */
-static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[CONFIG_MAX_SOCKET_UPD];
-static UINT8 deemphasis_list[CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET];
+static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET];
+static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET];
void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -119,12 +119,12 @@
unsigned int port, socket;
mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table;
- mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET_UPD;
+ mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET;
UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
(UPD_IIO_PCIE_PORT_CONFIG *)spr_iio_bifur_table;
/* Initialize non-zero default UPD values */
- for (socket = 0; socket < CONFIG_MAX_SOCKET_UPD; socket++) {
+ for (socket = 0; socket < MAX_SOCKET; socket++) {
for (port = 0; port < MAX_IIO_PORTS_PER_SOCKET; port++) {
PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */
PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */
@@ -134,10 +134,10 @@
}
mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list;
- mupd->FspmConfig.DeEmphasisNumber = CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET;
+ mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET;
UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list;
- for (port = 0; port < CONFIG_MAX_SOCKET_UPD * MAX_IIO_PORTS_PER_SOCKET; port++)
+ for (port = 0; port < MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; port++)
DeEmphasisConfig[port] = 0x1;
}