commit 76b8bc220122efd3774b0bddf5d2f229401fac46
author Angel Pons <th3fanbus@gmail.com> Thu Jul 23 02:32:27 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Sat Oct 24 15:44:14 2020 +0000
tree 09d8396d159a2e9b19163bc4b3cbf420cb6feede
parent 72f4dda6b7d1de5eef1df1d32be4595067c4a15d

nb/intel/haswell: Set up Root Complex topology

System BIOS must program some of the Root Complex Topology Capability
Structure registers located in configuration space, specs say. So do it.

Tested on Asrock B85M Pro4, still boots.

Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43744
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/haswell/haswell.h

diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 4bcaaa77..b160f83 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -20,6 +20,14 @@
 
 #include "registers/host_bridge.h"
 
+/* Device 0:1.0 PCI configuration space (PCIe Graphics) */
+
+#define PEG_DCAP2	0xc4	/* 32bit */
+
+#define PEG_ESD		0x144	/* 32bit */
+#define PEG_LE1D	0x150	/* 32bit */
+#define PEG_LE1A	0x158	/* 64bit */
+
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 
 #define MSAC		0x62	/* Multi Size Aperture Control */
@@ -59,6 +67,7 @@
 #define EPBAR8(x)  *((volatile u8  *)(DEFAULT_EPBAR + (x)))
 #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
 #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
+#define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x)))
 
 #include "registers/epbar.h"
 
@@ -69,6 +78,7 @@
 #define DMIBAR8(x)  *((volatile u8  *)(DEFAULT_DMIBAR + (x)))
 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
+#define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x)))
 
 #include "registers/dmibar.h"