tree 1ac4cfc74bcf53ae643880948412f97c3f015248
parent bbbdba1e50d1fa96708b4ce07f15a36b70244bbb
author Kevin Chiu <Kevin.Chiu@quantatw.com> 1601123668 +0800
committer Furquan Shaikh <furquan@google.com> 1601583335 +0000

mb/google/zork: Configure EMMC_RESET_L to drive high

Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.

Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>