commit 7686a56574a6773717b49a51786f301970d1c69c
author Vladimir Serbinenko <phcoder@gmail.com> Sun May 18 11:05:56 2014 +0200
committer Vladimir Serbinenko <phcoder@gmail.com> Tue Jul 29 00:52:28 2014 +0200
tree 40dcb474d1d0c88095e45c37044e25df5b6e2f20
parent b37ee1ee7c69836cfb333c13f787a1c3ba580b8f

sandy/ivybridge: Native raminit.

Based on damo22's work and my X230 tracing.

Works for my X230 in a variety of RAM configs.

Also-By: Damien Zammit <damien@zamaudio.com>
Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5786
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/northbridge/intel/sandybridge/Kconfig

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index f13b58d..2ceb945 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -33,7 +33,15 @@
 	select DYNAMIC_CBMEM
 	select CPU_INTEL_MODEL_306AX
 
-if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
+	bool
+	select CACHE_MRC_BIN
+	select MMCONF_SUPPORT
+	select MMCONF_SUPPORT_DEFAULT
+	select CPU_INTEL_MODEL_306AX
+	select HAVE_DEBUG_RAM_SETUP
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
 
 config VGA_BIOS_ID
 	string
@@ -50,7 +58,8 @@
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xff7e0000
+	default 0xff7e0000 if !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
+	default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
 
 config DCACHE_RAM_SIZE
 	hex