diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 9e6ca2a..b58dfd3 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -1,60 +1,5 @@
 config SOC_INTEL_CANNONLAKE_BASE
 	bool
-
-config SOC_INTEL_COFFEELAKE
-	bool
-	select SOC_INTEL_CANNONLAKE_BASE
-	select FSP_USES_CB_STACK
-	select HAVE_EXP_X86_64_SUPPORT
-	select HAVE_INTEL_FSP_REPO
-	select HECI_DISABLE_USING_SMM
-	select INTEL_CAR_NEM
-	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
-
-config SOC_INTEL_WHISKEYLAKE
-	bool
-	select SOC_INTEL_CANNONLAKE_BASE
-	select FSP_USES_CB_STACK
-	select HAVE_INTEL_FSP_REPO
-	select HECI_DISABLE_USING_SMM
-	select INTEL_CAR_NEM_ENHANCED
-	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
-
-config SOC_INTEL_COMETLAKE
-	bool
-	select SOC_INTEL_CANNONLAKE_BASE
-	select FSP_USES_CB_STACK
-	select HAVE_INTEL_FSP_REPO
-	select INTEL_CAR_NEM_ENHANCED
-	select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
-	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
-	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
-	select SOC_INTEL_COMMON_BASECODE
-	select SOC_INTEL_COMMON_BASECODE_RAMTOP
-
-config SOC_INTEL_COMETLAKE_1
-	bool
-	select SOC_INTEL_COMETLAKE
-
-config SOC_INTEL_COMETLAKE_2
-	bool
-	select SOC_INTEL_COMETLAKE
-
-config SOC_INTEL_COMETLAKE_S
-	bool
-	select SOC_INTEL_COMETLAKE
-
-config SOC_INTEL_COMETLAKE_V
-	bool
-	select SOC_INTEL_COMETLAKE
-
-config SOC_INTEL_CANNONLAKE_PCH_H
-	bool
-
-if SOC_INTEL_CANNONLAKE_BASE
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NHLT
 	select ARCH_X86
@@ -124,6 +69,58 @@
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	select X86_CLFLUSH_CAR
 
+config SOC_INTEL_COFFEELAKE
+	bool
+	select SOC_INTEL_CANNONLAKE_BASE
+	select FSP_USES_CB_STACK
+	select HAVE_EXP_X86_64_SUPPORT
+	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM
+	select INTEL_CAR_NEM
+	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+
+config SOC_INTEL_WHISKEYLAKE
+	bool
+	select SOC_INTEL_CANNONLAKE_BASE
+	select FSP_USES_CB_STACK
+	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM
+	select INTEL_CAR_NEM_ENHANCED
+	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+
+config SOC_INTEL_COMETLAKE
+	bool
+	select SOC_INTEL_CANNONLAKE_BASE
+	select FSP_USES_CB_STACK
+	select HAVE_INTEL_FSP_REPO
+	select INTEL_CAR_NEM_ENHANCED
+	select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
+	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
+	select SOC_INTEL_COMMON_BASECODE
+	select SOC_INTEL_COMMON_BASECODE_RAMTOP
+
+config SOC_INTEL_COMETLAKE_1
+	bool
+	select SOC_INTEL_COMETLAKE
+
+config SOC_INTEL_COMETLAKE_2
+	bool
+	select SOC_INTEL_COMETLAKE
+
+config SOC_INTEL_COMETLAKE_S
+	bool
+	select SOC_INTEL_COMETLAKE
+
+config SOC_INTEL_COMETLAKE_V
+	bool
+	select SOC_INTEL_COMETLAKE
+
+config SOC_INTEL_CANNONLAKE_PCH_H
+	bool
+
+if SOC_INTEL_CANNONLAKE_BASE
+
 config MAX_CPUS
 	int
 	default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE