##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

config NORTHBRIDGE_INTEL_I945GC
	bool
	select HAVE_DEBUG_RAM_SETUP

config NORTHBRIDGE_INTEL_I945GM
	bool
	select HAVE_DEBUG_RAM_SETUP

if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM

config VGA_BIOS_ID
	string
	default "8086,27a2"

config CHANNEL_XOR_RANDOMIZATION
	bool
	default n

config OVERRIDE_CLOCK_DISABLE
	bool
	default n
	help
	  Usually system firmware turns off system memory clock
	  signals to unused SO-DIMM slots to reduce EMI and power
	  consumption.
	  However, some boards do not like unused clock signals to
	  be disabled.

config MAXIMUM_SUPPORTED_FREQUENCY
	int
	default 0
	help
	  If non-zero, this designates the maximum DDR frequency
	  the board supports, despite what the chipset should be
	  capable of.

config CHECK_SLFRCS_ON_RESUME
	def_bool n
	help
	  On some boards it may be neccessary to hard reset early
	  during resume from S3 if the SLFRCS register indicates that
	  a memory channel is not guaranteed to be in self-refresh.
	  On other boards the check always creates a false positive,
	  effectively making it impossible to resume.

endif