drivers/amd/agesa: Don't save regular boot MTRR to flash
Save the regular boot MTRRs that are restored on the S3 path during
the CPU init in cbmem instead of storing them to the SPI flash.
This was probably done because historically this code run with late
cbmem init (in ramstage).
TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.
Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index d4191e3..4dadb0c 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -11,6 +11,7 @@
#define CBMEM_ID_ACPI_UCSI 0x55435349
#define CBMEM_ID_AFTER_CAR 0xc4787a93
#define CBMEM_ID_AGESA_RUNTIME 0x41474553
+#define CBMEM_ID_AGESA_MTRR 0xf08b4b9d
#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
#define CBMEM_ID_CBTABLE 0x43425442
@@ -89,6 +90,7 @@
{ CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \
{ CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \
{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
+ { CBMEM_ID_AGESA_MTRR, "AGESA MTRR " }, \
{ CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \
{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
{ CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 266fc89..8c383a5 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -50,7 +50,7 @@
config S3_DATA_SIZE
int
- default 8192
+ default 4096
endif # CPU_AMD_AGESA
diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c
index 10a8390..9220f3e 100644
--- a/src/drivers/amd/agesa/oem_s3.c
+++ b/src/drivers/amd/agesa/oem_s3.c
@@ -9,45 +9,24 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-typedef enum {
- S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type
- S3DataTypeMTRR ///< MTRR storage
-} S3_DATA_TYPE;
-
/* The size needs to be 4k aligned, which is the sector size of most flashes. */
-#define S3_DATA_MTRR_SIZE 0x1000
#define S3_DATA_NONVOLATILE_SIZE 0x1000
-#if CONFIG(HAVE_ACPI_RESUME) && \
- (S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
+#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE
#error "Please increase the value of S3_DATA_SIZE"
#endif
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len)
+static void get_s3nv_data(uintptr_t *pos, uintptr_t *len)
{
/* FIXME: Find file from CBFS. */
- u32 s3_data = CONFIG_S3_DATA_POS;
-
- switch (S3DataType) {
- case S3DataTypeMTRR:
- *pos = s3_data;
- *len = S3_DATA_MTRR_SIZE;
- break;
- case S3DataTypeNonVolatile:
- *pos = s3_data + S3_DATA_MTRR_SIZE;
- *len = S3_DATA_NONVOLATILE_SIZE;
- break;
- default:
- *pos = 0;
- *len = 0;
- break;
- }
+ *pos = CONFIG_S3_DATA_POS;
+ *len = S3_DATA_NONVOLATILE_SIZE;
}
AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock)
{
uintptr_t pos, size;
- get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
+ get_s3nv_data(&pos, &size);
u32 len = *(u32*)pos;
@@ -101,15 +80,12 @@
#endif
}
-__aligned((sizeof(msr_t))) static u8 MTRRStorage[S3_DATA_MTRR_SIZE];
-
AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock)
{
- u32 MTRRStorageSize = 0;
uintptr_t pos, size;
/* To be consumed in AmdInitResume. */
- get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
+ get_s3nv_data(&pos, &size);
if (size && dataBlock->NvStorageSize)
spi_SaveS3info(pos, size, dataBlock->NvStorage,
dataBlock->NvStorageSize);
@@ -127,24 +103,9 @@
}
/* Collect MTRR setup. */
- backup_mtrr(MTRRStorage, &MTRRStorageSize);
-
- /* To be consumed in restore_mtrr, CPU enumeration in ramstage. */
- get_s3nv_data(S3DataTypeMTRR, &pos, &size);
- if (size && MTRRStorageSize)
- spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize);
+ backup_mtrr();
return AGESA_SUCCESS;
}
#endif /* ENV_RAMSTAGE */
-
-const void *OemS3Saved_MTRR_Storage(void)
-{
- uintptr_t pos, size;
- get_s3nv_data(S3DataTypeMTRR, &pos, &size);
- if (!size)
- return NULL;
-
- return (void *)(pos + sizeof(UINT32));
-}
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index fea9d7c..51e8a4d 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
+#include <cbmem.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
@@ -42,10 +43,13 @@
TOP_MEM2,
};
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
+void backup_mtrr(void)
{
msr_t syscfg_msr;
- msr_t *mtrr_save = (msr_t *)mtrr_store;
+ msr_t *mtrr_save = (msr_t *)cbmem_add(CBMEM_ID_AGESA_MTRR,
+ sizeof(msr_t) * ARRAY_SIZE(msr_backup));
+ if (!mtrr_save)
+ return;
/* Enable access to AMD RdDram and WrDram extension bits */
syscfg_msr = rdmsr(SYSCFG_MSR);
@@ -59,14 +63,15 @@
syscfg_msr = rdmsr(SYSCFG_MSR);
syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, syscfg_msr);
-
- *mtrr_store_size = sizeof(msr_t) * ARRAY_SIZE(msr_backup);
}
void restore_mtrr(void)
{
msr_t syscfg_msr;
- msr_t *mtrr_save = (msr_t *)OemS3Saved_MTRR_Storage();
+ msr_t *mtrr_save = (msr_t *)cbmem_find(CBMEM_ID_AGESA_MTRR);
+
+ if (!mtrr_save)
+ return;
/* Enable access to AMD RdDram and WrDram extension bits */
syscfg_msr = rdmsr(SYSCFG_MSR);
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h
index 5f93d2a..183a330 100644
--- a/src/northbridge/amd/agesa/agesa_helper.h
+++ b/src/northbridge/amd/agesa/agesa_helper.h
@@ -38,7 +38,7 @@
void fixup_cbmem_to_UC(int s3resume);
void restore_mtrr(void);
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
+void backup_mtrr(void);
const void *OemS3Saved_MTRR_Storage(void);
#endif /* _AGESA_HELPER_H_ */