cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.
Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5f503da..25984f1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@
select POSTCAR_CONSOLE
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+ select NO_FIXED_XIP_ROM_SIZE
config PCIEXP_ASPM
bool