soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index d4b16c0..84425cc 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -95,6 +95,7 @@
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
+ select X86_CLFLUSH_CAR
config MAX_CPUS
int