diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3e128cd..63108de 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -85,7 +85,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	sandybridge_early_initialization();
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
 	s3resume = southbridge_detect_s3_resume();