| commit | 2678cd693a766f722e67c7d650a95e1d4a9af404 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Tue Aug 29 17:25:46 2017 +0530 |
| committer | Subrata Banik <subrata.banik@intel.com> | Wed Aug 30 15:45:14 2017 +0000 |
| tree | 5726ceee236bc4baddaf5e170133ea35cb18d613 | |
| parent | f10c8f9cf3930db624955f04cb6434d69e16030e [diff] |
soc/intel/cannonlake: Add PrmrrSize and C6DRAM config This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>