sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index ce81f76..1fde466 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -16,7 +16,6 @@
void usb_ehci_disable(pci_devfn_t dev)
{
u16 reg16;
- u32 reg32;
/* Set 0xDC[0]=1 */
pci_or_config32(dev, 0xdc, (1 << 0));
@@ -29,9 +28,9 @@
/* Clear memory and bus master */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable device */
switch (dev) {
@@ -56,7 +55,7 @@
bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
return;
- pci_cmd = pci_read_config32(dev, PCI_COMMAND);
+ pci_cmd = pci_read_config16(dev, PCI_COMMAND);
switch (slp_typ) {
case ACPI_S4: