commit | d9cb72559fa0f6251cc5144688da762daca1205f | [log] [tgz] |
---|---|---|
author | Reka Norman <rekanorman@google.com> | Tue Sep 27 16:08:08 2022 +1000 |
committer | Felix Held <felix-coreboot@felixheld.de> | Fri Sep 30 13:19:05 2022 +0000 |
tree | 23df5a1f4621a23cdc58711ac75df840b19f7336 | |
parent | a88d5e3bcafdbc8d2cc2491a04de839eef4f6a4e [diff] |
mb/google/nissa: Change TPM I2C freqeuncy to 1 MHz Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in the baseboard. Other nissa devices will be changed after verification. This saves 11 ms of boot time on nivviks and nereid. 400 kHz: 504:finished TPM initialization 272,304 (35,730) ... 512:finished TPM PCR extend 526,250 (23,729) 513:starting locking TPM 526,250 (0) 514:finished locking TPM 535,106 (8,855) 6:end of verified boot 543,927 (8,821) 1 MHz: 504:finished TPM initialization 266,293 (30,747) ... 512:finished TPM PCR extend 513,711 (20,108) 513:starting locking TPM 513,711 (0) 514:finished locking TPM 521,311 (7,599) 6:end of verified boot 528,893 (7,581) BUG=b:249201598 TEST=On nivviks and nereid, all timing requirements in the spec are met. Frequencies: nivviks - 972.01 kHz nereid - 968.99 kHz Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.