mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 34a785b..0a92efe 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -12,11 +12,20 @@
.backlight_pwm_hz = 200,
}"
- register "vr_slow_ramp_rate_set" = "3"
- register "vr_slow_ramp_rate_enable" = "1"
+ device cpu_cluster 0 on
+ chip cpu/intel/haswell
+ # Disable S0ix for now
+ register "s0ix_enable" = "0"
- # Disable S0ix for now
- register "s0ix_enable" = "0"
+ register "vr_config" = "{
+ .slow_ramp_rate_set = 3,
+ .slow_ramp_rate_enable = true,
+ }"
+
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
device domain 0 on
chip soc/intel/broadwell/pch